HLX6256 Datasheet, PDF (7/12 Pages) Honeywell Solid State Electronics Center – 32K x 8 STATIC RAM Low Power SOI

HLX6256
WRITE CYCLE AC TIMING CHARACTERISTICS (1)
Worst Case (3)
Symbol
Parameter
TAVAVW Write Cycle Time (4)
Typical
(2)
-55 to 125°C
Min
Max
25
Units
ns
TWLWH Write Enable Write Pulse Width
20
ns
TSLWH Chip Select to End of Write Time
20
ns
TDVWH Data Valid to End of Write Time
15
ns
TAVWH Address Valid to End of Write Time
20
ns
TWHDX Data Hold Time after End of Write Time
0
ns
TAVWL Address Valid Setup to Start of Write Time
0
ns
TWHAX Address Valid Hold after End of Write Time
0
ns
TWLQZ Write Enable to Output Disable Time
TWHQX Write Disable to Output Enable Time
12.6
ns
5
ns
TWHWL Write Disable to Write Enable Pulse Width (5)
5
ns
TEHWH Chip Enable to End of Write Time (6)
20
ns
(1) Test conditions: input switching levels, VIL/VIH=0V/3V, input rise and fall times <1 ns/V, input and output timing reference levels shown in the
Tester AC Timing Characteristics table, capacitive output loading >50 pF, or equivalent capacitive load of 5 pF for TWLQZ.
(2) Typical operating conditions: VDD=3.3 V, TA=25°C, pre-radiation.
(3) Worst case operating conditions: VDD=3.0 V to 3.6 V, -55 to 125°C, post total dose at 25°C.
(4) TAVAVW = TWLWH + TWHWL
(5) Guaranteed but not tested.
(6) Chip Enable (CE) pin not available on 28-lead FP or DIP.
TAVAVW
ADDRESS
NWE
TAVWL
TWHWL
DATA OUT
HIGH
IMPEDANCE
TWLQZ
TAVWH
TWLWH
TDVWH
TWHAX
TWHQX
TWHDX
DATA IN
DATA VALID
NCS
CE
TSLWH
TEHWH
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