HMC6352 Datasheet, PDF (3/13 Pages) Honeywell Solid State Electronics Center – Digital Compass Solution

HMC6352
Pin Descriptions
HMC6352
Pin Name
Description
1 OF-
No User Connection (Offset Strap Negative)
2 SR+
No User Connection (Set/Reset Strap Positive)
3 NC
No User Connection
4 NC
5 GND
No User Connection
Supply/System Ground
6 NC
No User Connection
7 SDI
I2C Data Output (SPI Data In)
8 SDO
No User Connection (SPI Data Out)
9 PGM
No User Connection (Program Enable)
10 SCL
I2C Clock (SPI Clock)
11 SS
No User Connection (Slave Select)
12 NC
No User Connection
13 NC
No User Connection
14 VDD
Supply Voltage Positive Input (+2.7VDC to +5.0VDC)
15 NC
No User Connection
16 NC
No User Connection
17 NC
No User Connection
18 NC
No User Connection
19 CB2
Amplifier B Filter Capacitor Connection
20 CB1
Amplifier B Filter Capacitor Connection
21 NC
No User Connection
22 CA2
23 CA1
24 OF+
Amplifier A Filter Capacitor Connection
Amplifier A Filter Capacitor Connection
No User Connection (Offset Strap Positive)
I²C Communication Protocol
The HMC6352 communicates via a two-wire I²C bus system as a slave device. The HMC6352 uses a layered protocol
with the interface protocol defined by the I²C bus specification, and the lower command protocol defined by Honeywell.
The data rate is the standard-mode 100kbps rate as defined in the I²C Bus Specification 2.1. The bus bit format is an 8-bit
Data/Address send and a 1-bit acknowledge bit. The format of the data bytes (payload) shall be case sensitive ASCII
characters or binary data to the HMC6352 slave, and binary data returned. Negative binary values will be in two’s
complement form. The default (factory) HMC6352 7-bit slave address is 42(hex) for write operations, or 43(hex) for read
operations.
The HMC6352 Serial Clock (SCL) and Serial Data (SDA) lines do not have internal pull-up resistors, and require resistive
pull-ups (Rp) between the master device (usually a host microprocessor) and the HMC6352. Pull-up resistance values of
about 10k ohms are recommended with a nominal 3.0-volt supply voltage. Other values may be used as defined in the I²C
Bus Specification 2.1.
The SCL and SDA lines in this bus specification can be connected to a host of devices. The bus can be a single master to
multiple slaves, or it can be a multiple master configuration. All data transfers are initiated by the master device which is
responsible for generating the clock signal, and the data transfers are 8 bit long. All devices are addressed by I²C’s
unique 7 bit address. After each 8-bit transfer, the master device generates a 9 ^th clock pulse, and releases the SDA line.
The receiving device (addressed slave) will pull the SDA line low to acknowledge (ACK) the successful transfer or leave
the SDA high to negative acknowledge (NACK).
Per the I²C spec, all transitions in the SDA line must occur when SCL is low. This requirement leads to two unique
conditions on the bus associated with the SDA transitions when SCL is high. Master device pulling the SDA line low while
the SCL line is high indicates the Start (S) condition, and the Stop (P) condition is when the SDA line is pulled high while
the SCL line is high. The I²C protocol also allows for the Restart condition in which the master device issues a second
start condition without issuing a stop.
All bus transactions begin with the master device issuing the start sequence followed by the slave address byte. The
address byte contains the slave address; the upper 7 bits (bits7-1), and the Least Significant bit (LSb). The LSb of the
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