HMC5843 Datasheet, PDF (15/19 Pages) Honeywell Solid State Electronics Center – 3-Axis Digital Compass IC

HMC5843
DYRA7 DYRA6 DYRA5 DYRA4 DYRA3 DYRA2 DYRA1 DYRA0
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
DYRB7 DYRB6 DYRB5 DYRB4 DYRB3 DYRB2 DYRB1 DYRB0
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
Table 18: Data Output Y Registers A and B
Data Output Z Registers A and B
The data output Z registers are two 8-bit registers, data output register A and data output register B. These registers
store the measurement result from channel Z. Data output Z register A contains the MSB from the measurement result,
and data output Z register B contains the LSB from the measurement result. The value stored in these two registers is a
16-bit value in 2’s complement form, whose range is 0xF800 to 0x07FF. DZRA0 through DZRA7 and DZRB0 through
DZRB7 indicate bit locations, with DZRA and DZRB denoting the bits that are in the data output Z registers. DZRA7 and
DZRB7 denote the first bit of the data stream. The number in parenthesis indicates the default value of that bit.
In the event the ADC reading overflows or underflows for the given channel, or if there is a math overflow during the bias
measurement, this data register will contain the value -4096 in 2’s complement form. This register value will clear when
after the next valid measurement is made.
DZRA7 DZRA6 DZRA5 DZRA4 DZRA3 DZRA2 DZRA1 DZRA0
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
DZRB7 DZRB6 DZRB5 DZRB4 DZRB3 DZRB2 DZRB1 DZRB0
(0)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
Table 19: Data Output Z Registers A and B
Data Output Register Operation
When one or more of the output registers are read, new data cannot be placed in any of the output data registers until all
six data output registers are read. This requirement also impacts DRDY and RDY, which cannot be cleared until new
data is placed in all the output registers.
Status Register
The status register is an 8-bit read-only register. This register is used to indicate device status. SR0 through SR7
indicate bit locations, with S R denoting the bits that are in the status register. SR7 denotes the first bit of the data stream.
SR7
SR6
SR5
SR4
SR3
SR2
SR1
SR0
(0)
(0)
(0)
(0)
(0)
REN (0) LOCK (0) RDY(0)
Table 20: Status Register
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