HMX2000 Datasheet, PDF (1/2 Pages) Honeywell Solid State Electronics Center – MIXED SIGNAL SOI GATE ARRAYS

MIXED SIGNAL SOI GATE ARRAYS
HMX2000
FAMILY
Features
x Fabricated on Honeywell’s RICMOS^TM IV Silicon
On Insulator (SOI) process
- 0.8 Pm Process (L_eff = .65 Pm)
x HMX2000 supports 5V operation
x TTL, CMOS, Cold Spare compatible I/O
x 3 or 4 layer metal interconnect
x Compatible with existing HX2000 digital gate arrays
- Sea-Of-Gates flow around embedded cells
- Memory, A/D, D/A and other cores available
x Up to 275,000 gates useable
x Typical gate toggle power 0.6 PW/MHz/gate
x Analog on SOI provides 10dB lower substrate noise
than bulk CMOS at 1GHz, 25dB lower at 100 MHz
x NMOS F_t = 15 GHz
x CrSi resistor, 2500:/square r 20%
- 300 ppm/qC temperature coefficient
x Linear Capacitors
- 100ppm/Volt, 0.5fF/Pm²
x Vt~0.8V
x DMOS: NMOS AND PMOS > 20 Volts Breakdown
x Lateral Bipolar: ǃ>20
x Inductors (Metal Spiral) Q~2-5, 2-5nH
x Body terminal fully oxide-isolated from substrate
x Ring Oscillator Speed ~ 150 psec/stage
x Total Dose Hardness > 1M Rad(Si)
x No Latchup
Future enhancements
x 3.3V digital supply and I/O
General Description
The HMX2000 family of arrays incorporate Mixed Signal
capability as an extension of the available HX2000 Gate
Array family, fabricated on Honeywell’s RICMOS^TM IV
Silicon On Insulator (SOI) process. The SOI-IV process at
Honeywell has performance advantages over bulk silicon
CMOS in that 25% to 35% higher speeds can be obtained
or up to 30% lower power. The SOI substrate can support a
6X improvement in static noise margins and significantly
lower subthreshold leakage current.
Each HMX2000 array design is founded on our proven
SOI ASIC library of SSI and MSI logic elements, available
core IP (intellectual property), integratable passives, and
selectable I/O pads. This family is fully compatible with
Honeywell’s range of high reliability screening, test and
packaging options.
Designers can choose from a wide variety of I/O types.
Output buffer options include 8 drive strengths,
CMOS/TTL levels, IEEE 1149.1 boundry scan, pull-
up/pull-down resistors, and tri-state capability. Input
buffers can be selected for CMOS/TTL/Schmitt trigger
levels, IEEE 1149.1 boundry scan and pull-up/pull-down
resistors. Bi-directional buffers are also available.
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Solid State Electronics Center x 12001 State Highway 55, Plymouth, MN 55441x [phone] x http://www.ssec.honeywell.com