HI-6137 Datasheet, PDF (95/230 Pages) Holt Integrated Circuits – 40 MHz SPI Host Interface

HI-6137
13. REMOTE TERMINAL REGISTERS
In addition to the registers described here, the RT can also utilize one or more Memory Address Pointer registers (de-
scribed in Section 9.12) for managing SPI read/write operations.
13.1. Remote Terminal Configuration Register (0x0017)
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MR Reset
RW
Host Access
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit
Bit No. Mnemonic
15 − 14 RTTO1:0
13 RTINHA
12 RTINHB
R/W Reset Function
RT-RT Time Out Select.
This 2-bit field selects the “no response” time-out delay for RT-to-RT
receive commands from four available selections:
Bit 15:14
Bus Dead Time
RT-RT Time Out
00
R/W 0
01
10
11
15μs
20μs
58μs
138μs
57μs
62μs
100μs
180μs
For RT-RT commands, time out delay is measured per Figure 8 in the
RT Validation Test Plan, SAE AS4111. That is, from mid-parity of the
receive command to mid-sync of the first received data word. This
interval includes 20µs each for the embedded transmit command word
and transmit-RT status word within this span.
RT Bus A Inhibit.
If this bit is logic 1, Bus A is inhibited, as defined by the BSDTXO bit in
“Master Configuration Register 1 (0x0000)”. The BSDTXO bit offers two
R/W 0 options: inhibit transmit and receive, or inhibit only transmit.
Note: If this bit is logic 0, Bus A is not inhibited here but its operation
may otherwise be globally inhibited by logic 1 at the TXINHA pin, or logic
1 at the TXINHA bit in the “Master Status and Reset Register (0x0001)”.
RT Bus B Inhibit.
If this bit is logic 1, Bus B is inhibited, as defined by the BSDTXO bit in
“Master Configuration Register 1 (0x0000)”. The BSDTXO bit offers two
R/W 0 options: inhibit transmit and receive, or inhibit only transmit.
Note: If this bit is logic 0, Bus B is not inhibited here but its operation
may otherwise be globally inhibited by logic 1 at the TXINHB pin, or logic
1 at the TXINHB bit in the “Master Status and Reset Register (0x0001)”.
HOLT INTEGRATED CIRCUITS
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