HI-6120_15 Datasheet, PDF (92/162 Pages) Holt Integrated Circuits – MIL-STD-1553 Remote Terminal ICs

HI-6120, HI-6121
11.6. Circular Buffer Mode 2
Circular Buffer Mode 2 segregates message data and
message information in separate host-defined buffers.
Separating data from message information simplifies
the host software that loads or unloads the data to or
from the buffer. After a predetermined number of mes-
sages has been transacted, buffer address pointers for
data and message information are automatically reset to
their base addresses. Figure 16 is a generalized illustra-
tion of Circular Buffer Mode 2, while Figure 17 shows a
specific example.
Circular Buffer Mode 2 is selected when the Control
Word PPEN bit is zero and the CIR2EN bit is logic 1.
When the CIR2EN bit is high, the CIR1EN bit is don’t
care. The descriptor Control Word DPB bit is not used.
Any receive subaddress using circular buffer mode 2
has two circular buffers: a data storage buffer and a
message information buffer. A separate buffer pair may
be used for transmit commands to the same subad-
dress, if it also uses circular buffer mode 2. Each trans-
mit and receive subaddress using circular buffer mode
2 may have unique data buffer and message info buffer
assignments. Careful management (involving the bus
controller) may allow buffer sharing, as long as multiple
message sequences to a given subaddress are not in-
terrupted by messages to other subaddresses that use
the same buffer space.
When a subaddress uses circular buffer mode 2, its De-
scriptor Table 4-word block is defined as follows:
Descriptor Word 1
Descriptor Word 2
Descriptor Word 3
Descriptor Word 4
Control Word
SA (Buffer Start Address)
CA (Buffer Current Address)
MIBA (Message Info Buffer Addr)
If Descriptor Word 1 is stored at memory address N, De-
scriptor Word 2 is stored at address N+1, and the other
two words are stored at addresses N+2 and N+3. The
first word in the descriptor block is the Control Word. The
second and third words in the descriptor are the Start
Address (SA) and Current Address (CA) pointers. The
Message Information Buffer Address (MIBA) points to
the storage location for the Message Information Word
from the next occurring message.
Each time a message is completed, the device writes
a new Message Information Word and Time-Tag Word
in the MIB (Message Information Buffer) at the MIBA
address and following location, respectively. The MIBA
pointer is not updated if message error occurred, if the
Busy status bit was set, or if the command was illegal-
ized (for example an illegal word count expressed in the
command word.) For these situations, the Message In-
formation and Time-Tag words are still written, but MIB
updates for the following message will overwrite the
just-written Message Information and Time-Tag word
addresses.
For error-free receive messages, received data words
are stored in the data buffer after message completion,
starting at the CA address value. The CA value is then
updated for next-message readiness.
After writing the two MIB words, the device updates the
MIBA value to show the buffer address to be used by
the next message. Until the predetermined number of
error-free messages is transacted, the MIBA value is
double-incremented at each update. Before updating
the MIBA in Descriptor Word 4, the pre-existing MIBA
value is incremented once then checked for ‘full count,”
occurring when all N low-order address bits initialized to
zero (explained below) become N “one” bits. Full count
means the predetermined number of successful mes-
sages was completed. When this occurs, the CA and
MIB pointers are automatically written to their initialized
values by the device.
To preserve data integrity, the TRXDB bit should be set
in Control Register 2 to avoid storing incomplete data
from messages resulting in error. With TRXDB asserted,
the host is not bothered by message retries caused by
errors. The Buffer Empty/Full interrupt (if enabled) is
generated only upon successful transaction of the entire
N-message data block.
To initialize Circular Buffer Mode 2, the host must know
the number of messages to be transacted, always a
power of two: 1, 2, 4, 8, 16, 32, 64, 128, 256 or 512
messages. The host writes descriptor Control Word bits
7:4 with an encoded 4-bit value to set the fixed number
of messages to be transacted. This is illustrated in Table
8. The host initializes the descriptor block MIBA pointer
with a Message Information Buffer starting address.
Because the MIB stores two words for each message,
the allocated MIB space should equal 2x the number of
messages.
The initially-loaded MIB base address value is restricted.
Some lower bits of the starting address must be zero so
the device can restore the MIBA pointer to the initial MIB
base address after the predetermined message count is
transacted. As illustrated in Table 8, the required number
of logic-0 bits depends on the message count. Initializ-
ing the MIBA base address with more trailing zeros than
indicated is acceptable; initializing less trailing zeros will
cause malfunction.
HOLT INTEGRATED CIRCUITS
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