HI-6120_15 Datasheet, PDF (62/162 Pages) Holt Integrated Circuits – MIL-STD-1553 Remote Terminal ICs

HI-6120, HI-6121
Bit No. Mnemonic R/W Reset Function
11 DBAC
0
SR = 0
Descriptor Block Accessed.
Internal device logic asserts the DBAC bit upon completion of message
processing. The host may poll this bit to detect subaddress activity, instead of
using host interrupts. This bit is reset to logic zero by MR master reset, SRST
software reset or a read cycle to this memory address.
10 DPB
0
SR = 0
Data Pointer B.
This status bit is maintained by the device and only applies in ping-pong
buffer mode. This bit indicates the buffer to be used for the next occurring
transmit command to this subaddress. When the DPB bit is logic 0, the next
message will use Data Pointer A; when DPB is logic 1, the next message
uses Data Pointer B. In ping-pong buffer mode, the bit is inverted after each
error-free message completion. The DPB bit is not altered after messages
ending in error, after illegal commands or after messages when the terminal
responds with Busy status. This bit is reset to logic 0 by MR master reset or
SRST software reset; therefore the first message received after either reset
will use Buffer A. This bit is “don’t care” for indexed single-buffer mode or
either circular buffer mode.
9 BCAST
0
SR = 0
Broadcast Received.
The device sets this bit when a broadcast-transmit command is received
for this subaddress. Because non-mode broadcast-transmit commands
are always illegal, the assertion of this bit in the Control Word by the de-
vice indicates an illegal command was received. Terminal response varies,
depending on whether or not illegal command detection applies (any bits set
in Illegalization Table). This bit has no function if the BCSTINV bit is asserted
in Configuration Register 1; in this case commands to RT address 31 are not
recognized as valid by the device. This bit is reset to logic 0 by MR master
reset or SRST software reset.
8 PPON
Ping-Pong Enable Acknowledge.
This bit is controlled by the device and should not be written by the host. It
only applies if PPEN bit 2 was initialized to logic one by the host after reset,
enabling ping-pong buffer mode for this subaddress. The RT asserts this
bit when it recognizes ping-pong is active for this subaddress. Before load-
ing the transmit data buffer for this subaddress, the host can ask the RT to
temporarily disable ping-pong by asserting STOPP bit 3. The RT acknowl-
0 edges ping-pong is disabled by negating PPON. The host can safely load the
buffer without data collision while PPON is negated. After buffer servicing, the
host asks the RT to re-enable ping-pong by negating STOPP bit 3. The RT
acknowledges ping-pong is re-enabled by asserting PPON.
If PPEN bit 2 is high and PPON bit 8 is low when new commands arrive for
this subaddress, ping-pong is disabled. Each new message transmits data
from the same buffer, specified by DPB bit 10, and the DPB bit does not
toggle after command completion.
7-4 CIR2ZN
Circular Mode 2 Zero Number.
0 ^{Used only in circular buffer mode 2, this 4-bit field is initialized with the}
number of trailing zeros in the initialized MIBA address. This is explained in
Section 11.6, which fully describes circular buffer mode 2.
HOLT INTEGRATED CIRCUITS
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