HI-6136_16 Datasheet, PDF (79/206 Pages) Holt Integrated Circuits – Compact Multi-Terminal Device with SPI Host Interface

HI-6136
Bit No. Mnemonic
3
BUSY
2
SSYSF
1
DBCA
0
TF
R/W Reset Function
Busy status bit.
The host maintains this read-write bit. When set, the RT asserts its
Busy bit in status response for all valid commands. Instead of enabling
Busy for all commands, the host can assert Busy status for selected
commands by asserting the Busy bit in descriptor table Control Words
for the individual commands. When response to a command conveys
R/W
0
Busy status, the RT suppresses transmission of data words that would
normally accompany status for transmit commands. For messages
transacted with Busy status, the WASBSY flag is asserted in the stored
Message Information Word. If INTBUSY bit 2 is set in the “Extended
Configuration Register (0x004D)”, the WASBUSY bit 9 is also enabled in
the RT Interrupt Information Word.
Note: Busy status alone is not an interrupt event. See “Extended
Configuration Register (0x004D)” on page 41.
Subsystem Fail status bit.
The host maintains this read-write bit. This register bit is logically ORed
with the RTSSF input pin. If either SSYSF register bit or RTSSF pin
R/W
0
is asserted, the SSYSF Subsystem Flag status bit is set. If the RT’s
Configuration Register MCOPT1 bit equals 0, reception of a “transmit
vector word” mode command (MC16) causes automatic reset of the
SSYSF status bit in this register; when this occurs, the register bit is
reset before status word transmission begins.
Dynamic Bus Control Acceptance status bit.
R/W
0
The host maintains this read-write bit. If the terminal is to acknowledge a
Dynamic Bus Control, Mode Code 0 command, the host should set this
bit to a “1”.
Terminal Flag status bit.
The host maintains this read-write bit. When this bit is asserted, the
R/W
0
Terminal Flag status bit is set. If the Terminal Flag bit is set while
responding to subaddress transmit commands or mode code commands
16-31 that normally transmit a data word, all data word transmission is
suppressed.
13.7. Remote Terminal Current Message Information Word Register (0x001B)
MSB
Register Value
LSB
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MR Reset
R
Host Access
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit
This 16-bit register is Read-Only and is fully maintained by the device. This register is cleared after MR pin master reset,
but is unaffected by assertion of RTRESET remote terminal software reset in the “Master Status and Reset Register
(0x0001)”. This register contains the data buffer address (assigned in the terminal’s Descriptor Table) corresponding
to the last decoded valid command’ for the Remote Terminal. This register is updated 5µs after the ACTIVE output is
asserted.
HOLT INTEGRATED CIRCUITS
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