HI-6136_16 Datasheet, PDF (154/206 Pages) Holt Integrated Circuits – Compact Multi-Terminal Device with SPI Host Interface

HI-6136
19. SELF-TEST
The HI-6136 provides several host-directed RAM self-tests, as well as an automatic (but optional) RAM self-test
performed after Master Reset. In addition, on-line analog and off-line digital transmit/receive loopback tests are
provided for RT terminal mode.
19.1. Optional RAM Self-Test after Hardware Master Reset
When the MTSTOFF input pin is logic 0, the device automatically performs RAM self-test after each hardware master
reset, following the rising edge of MR input signal. See Section “18.1. Hardware Master Reset and Optional Auto-
Initialization”. The READY output pin goes low at MR assertion. READY remains low after MR rising edge and during
RAM self-test. The RAM self-test performed is the increment/decrement (Inc/Dec) method described on page 159.
When successful RAM self-test is complete, the READY output pin goes high, indicating that device registers and
RAM can be configured for operation. The entire RAM address space from 0x0052 to 0x1FFF is cleared to 0x0000.
RAM self-test after hardware master reset is optional. If the MTSTOFF input pin is logic 1, RAM testing is skipped,
speeding up READY assertion. Table 13 on page 147 shows the reset timing options.
19.2. Host-Directed Self-Test
The device supports host-directed RAM self-test (sometimes called RAM built-in self-test, or RAM BIST) and single-
word transmit/receive loopback, which may be off-line digital or on-line analog. Host-directed self-test is configured
and operated using register read/write operations.
The host initiates self-test mode by asserting the TEST input pin to logic 1. When the TEST pin is high, four registers
are active for performing RAM self-test or RT mode loopback self-tests:
19.2.1. Self-Test Control Register (0x0028)
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MR Reset
RW
R
RW
R Host Access
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit
The function of this register is multiplexed by the device TEST input pin. When the TEST pin is logic 0 (normal
operating mode), register address 0x0028 has no function.
When the TEST input pin is logic 1, register address 0x0028 functions as the Self-Test Control Register, a Read-Write
register used for RAM memory testing, or analog or digital loopback tests. Bits 0, 1, 8, 9 are Read-Only. The remaining
bits in this register are Read-Write.
After test completion, the TEST input pin should be reset to logic 0, restoring all register bits to Read-Write.
Descriptions below apply when the TEST input pin is logic 1; the register is operating as the Self-Test Control Register.
This register supports two types of test: Register bits 15 - 8 are used for RAM built-in self test (RAM BIST). Register
bits 7 - 2 are used for transceiver loopback testing (either digital loopback or analog loopback).
Under internal logic control, this device uses one RAM self test (Inc / Dec Test described below) to check internal
RAM memory after every MR pin master reset, unless the MTSTOFF input pin is logic 1. This option may be used to
speed up reset completion. Self-Test Control Register bits 15 - 8 provide a means for the host to perform RAM self-
test at other times. Register bits 13:11 select RAM test type. Then bit 10 assertion starts the selected RAM test, and
bits 9-8 report a pass/fail result after test completion. All tests are destructive, overwriting data present before test
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