HI-6137_16 Datasheet, PDF (176/230 Pages) Holt Integrated Circuits – Compact Multi-Terminal Device with SPI Host Interface

HI-6137
18.5. MIL-STD-1760: Busy Status Assertion After Power-Up
A MIL-STD-1760 RT must be able to respond on the bus within 150ms following power turn-on. Between power-on
and 150ms, it is acceptable for the RT to respond with the “Busy” bit set in the RT Status Word (see Section 13.6 on
page 102). This indicates the RT is awake but not ready to transfer data. Alternatively, the RT may respond Clear
Status with valid data.
In order to engage 1760 mode, the pin MODE1760 is asserted during a hardware reset. The pin status will be latched
200ns after the rising edge of MR Master Reset (the same time as the RT address). During 1760 mode, the device will
respond to any valid command (with matching RT address) with the BUSY bit set in the status word. No data words
will be transmitted and no interrupts or logging of data will occur. Mode 1760 operation may be confirmed by the host
by reading Mode 1760 Status bit 7 in “Master Configuration Register 2 (0x004E)”.
Within 500ms following power turn-on, the MIL-STD-1760 RT must respond with data as defined by the MIL-STD-1760
standard, with “Busy” status bit reset. The RT host processor must be fully operational at this time. After system
initialization is complete, the host can deactivate 1760 mode by writing “1” to bit 7 in “Master Configuration Register 2
(0x004E)”. Alternatively, bit 4 RTSTEX and bit 6 RTENA in “Master Configuration Register 1 (0x0000)” may be written
“1” either by the host or by EEPROM auto initialization (see “Hardware Master Reset and Optional Auto-Initialization”).
HOLT INTEGRATED CIRCUITS
176