HI-6137_16 Datasheet, PDF (122/230 Pages) Holt Integrated Circuits – Compact Multi-Terminal Device with SPI Host Interface

HI-6137
Command
Sync
RT Addr
TA4:0
T/R ^{Subaddress Word Count}
Bit SA4:0
WC4:0
P
Command RT Addr _T/R Subaddress Mode Code
Sync
TA4:0 Bit SA4:0
MC4:0
P
0x04
Descriptor Address Format
Depends On
Command Word’s Subaddress
0x05
00000100
00
00000101
00
Descriptor Table Address
for Subaddress Commands
SA4:0 equals 00001 to 11110
Descriptor Table Address
for Mode Code Commands
SA4:0 equals 00000 or 11111
Figure 12.  Deriving a Descriptor Table Control Word Address From Command Word
(assumes table base address = 0x0400)
14.4.1. Receive Subaddress Control Word
Receive Subaddress Control Words apply when a valid command word T/R bit equals zero (receive) and the subaddress
field has a value in the range of 1 to 30 (0x1E). The descriptor Control Word defines terminal command response
and interrupt behavior, and conveys activity status to the host. It is initialized by the host before terminal execution
begins. If using ping-pong data buffers, Control Words should only be written when the RTENA bit is set in the “Master
Configuration Register 1 (0x0000)”. Failure to meet this requirement prevents automatic assertion of PPON bit 8 when
PPEN bit 2 is set, and successive messages will repeatedly use the same buffer. Bits 8-11 cannot be written by the
host; these bits are updated by the device during terminal execution, that is, when the “Master Configuration Register
1 (0x0000)” RTSTEX bit equals 1. The host can write bits 0-2 and 4-7 only when RSTEX equals zero; bits 3 and 12-
15 can be written anytime. This register is cleared to 0x0000 by MR master reset. Software reset (SRST) clears just
the DBAC, DPB and BCAST bits. Following any read cycle to the Control Word address, the DBAC bit is reset.
MKBUSY
H H H H D1 D D D H H H H H H H H
MSB 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 LSB
H Bit maintained by host
D Bit maintained by device
D1 Bit set by device, reset by host read cycle
NOTE: ‘Reset’ refers to bit value following Master Reset (MR). The bit value following software reset is
unchanged unless specifically indicated by an “SR” value.
HOLT INTEGRATED CIRCUITS
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