HI-6135_16 Datasheet, PDF (13/172 Pages) Holt Integrated Circuits – Compact Remote Terminal with SPI Host Interface

HI-6135
Pin
MODE1760
LOCK
RTMC8
RTSSF
IRQ
ACKIRQ
RTA4:0
RTAP
BENDI
TEST
TESTA
Function
Input
50kΩ pull-down
Input
50kΩ pull-down
Output
Open-Drain
Input
50kΩ pull-down
Output
Open-Drain
Input
50kΩ pull-down
Inputs
50kΩ pull-ups
Input
50kΩ pull-down
Input
50kΩ pull-down
Input
50kΩ pull-down
Description
Mode 1760 enable, active high. Assert this pin during a hardware reset to enable
1760 mode. During 1760 mode, the device will respond to any valid command
(with matching RT address) with the BUSY bit set in the status word. No data
words will be transmitted and no interrupts or logging of data will occur.
Pin states are latched to the Lock bit in the RT Operational Status Register (see
page 45) when rising edge occurs on the MR pin. If status register Lock bit
is high, the host cannot overwrite the terminal address in the same register. If
status register Lock bit is low, the host can overwrite the terminal address and
parity (and the Lock bit) in the RT Operational Status register.
Remote Terminal “Reset RT” mode command (MC8) received. This active low
output is asserted at Status Word completion when the RT received a “Reset
Remote Terminal” mode code command. The minimum output pulse width is
100ns, unaffected by MR assertion.
RT Subsystem Fail input, active high. When this input is high, the RT sets the
Subsystem Fail flag in its transmit status word. This input is logically-ORed with
the SSYSF bit in the RTs 1553 Status Word Bits Register.
Interrupt request, active low. This pin is asserted each time an enabled interrupt
event occurs. This signal is programmed as a brief low-going pulse output or
as a level output by the INTSEL bit in the “Master Configuration Register 1
(0x0000)”. If level output is selected, IRQ stays low until the host acknowledges
IRQ by pulsing a rising edge at the ACKIRQ pin.
Interrupt Acknowledge, active high. This input is only used when the INTSEL bit
in the RT Configuration Register is high, enabling level interrupt assertion for the
IRQ pin. When interrupt assertion causes the IRQ pin to go low, a high-going
pulse on ACKIRQ (250ns minimum duration) clears the IRQ output to logic 1.
Remote terminal address bits 4 - 0 and parity bit. The RTAP pin provides odd
parity for the address on pins RTA4:0.
The terminal address and parity pin levels are latched into the RT Operational
Status Register (see page 45) when rising edge occurs on the MR pin. The
RT Operational Status Register value (not these pins) reflects the active terminal
address. The host can overwrite the RT Operational Status register address
value only when the register Lock bit is reset.
Big Endian configuration pin for selecting “endianness” or byte order, when
using byte transfers. Endianness is the system attribute that indicates whether
integers are represented with the most significant byte stored at the lowest
address (big endian) or at the highest address (little endian). Internal register /
RAM storage is “big endian.”
This pin controls the byte order of transferred 16-bit data following the SPI
command. When BENDI is low, “little endian” is chosen; the low order byte (bits
7:0) is transacted on the SPI before the high order byte (bits 15:8). When BENDI
is high, “big endian” is chosen and the high order byte is transacted on the SPI
before the low order byte.
Test enable input. The host asserts this pin to perform RAM self-test and loop-
back tests.
Pin used for factory test. Do not connect.
HOLT INTEGRATED CIRCUITS
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