HI-6135_16 Datasheet, PDF (112/172 Pages) Holt Integrated Circuits – Compact Remote Terminal with SPI Host Interface

HI-6135
14. SERIAL EEPROM PROGRAMMING UTILITY
The HI-6135 can program a serial EEPROM via the dedicated EEPROM SPI port for subsequent auto-initialization
events. The device copies host-configured registers and RAM (configuration tables and possibly data buffers) to serial
EEPROM.
Compatible SPI serial EEPROMs are 3.3V, operate in SPI modes 0 or 3 and have 128-byte pages. The serial SPI data
is clocked at 8.3 MHz SCK frequency. A 2K x 8 EEPROM can restore the lower 1K x 16 device address space. A 16K
x 8 EEPROM retains the entire 8K x 16 register/RAM address space.
14.1. Writing the Auto-Initialization EEPROM
A deliberate series of events initiates copy of data from registers and RAM to serial EEPROM. This reduces the likelihood
of accidental EEPROM overwrites. Note: The RT address must have correct (odd) parity before EEPROM read or
write can occur. The following series of events must occur to initiate programming:
1. Using a fresh host initialization immediately following MR master reset as the basis for EEPROM copy
Until EEPROM reprogramming is complete, disconnect the terminal from MIL-STD-1553 buses, or take other
measures to prevent bus activity detection by the device. With the AUTOEN, TXINHA and TXINHB pins in logic
0 state, apply MR master reset and wait for READY output assertion. Verify that the IRQ interrupt output does
not pulse low at READY assertion, indicating likely RT address parity error at the RTA4:0 and RTAP pins. Using
known good parameters, the host initializes device registers, the RAM descriptor table and transmit data buffers
(if necessary).
• RTENA bit in “Master Configuration Register 1 (0x0000)” should be logic 1, but RTSTEX register bit 4 must
remain in the post-reset logic 0 state.
2. Using the existing EEPROM configuration as the baseline for a new EEPROM configuration
Until EEPROM reprogramming is complete, disconnect the terminal from MIL-STD-1553 buses, or take other
measures to prevent bus activity detection by the device. With the AUTOEN pin in logic 1 state and the TXINHA
and TXINHB pins in logic 0 state, apply and release MR master reset and wait for READY output assertion. Verify
that the IRQ output does not pulse low (or go and remain low) at READY assertion. Confirm that the EECKE and
RAMIF bits are logic 0 in the “Master Status and Reset Register (0x0001)”. If register bit 4 (RTSTEX) in “Master
Configuration Register 1 (0x0000)” was set by auto-initialization, reset it now. Modify register and RAM values to
reflect the new changes.
EEPROM programming is locked out at step 3 for the following conditions:
• ACTIVE output pin assertion occurs after MR master reset.
• RTSTEX bit 4 is set in “Master Configuration Register 1 (0x0000)”.
3. The host writes a 2-part “unlock code” to RAM address 0x0051. The unlock code value selectively enables the
terminal to automatically start execution, after subsequent auto-initialization sequences are performed. Unlock
words are encoded as shown in Table 7.
Table 7.  Terminal Unlock Word Encoding
Word 1
0xA00A
0xA03A
Word 2
0x5FF5
0x5FC5
Initialize RT ²
No auto init. ¹
X
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