HT45F4MA Datasheet, PDF (82/145 Pages) Holtek Semiconductor Inc – Power Bank Flash MCU

HT45F4MA/HT45FH4MA/HT45FH4MA-1
Power Bank Flash MCU
Bit 3
Bit 2
Bit 1
Bit 0
T1OC: TP1_0, TP1_1 output control bit
Compare Match Output Mode
0: Initial low
1: Initial high
PWM Mode/Single Pulse Output Mode
0: Active low
1: Active high
This is the output control bit for the TM output pin. Its operation depends upon
whether TM is being used in the Compare Match Output Mode or in the PWM Mode/
Single Pulse Output Mode. It has no effect if the TM is in the Timer/Counter Mode. In
the Compare Match Output Mode it determines the logic level of the TM output pin
before a compare match occurs. In the PWM Mode it determines if the PWM signal is
active high or active low.
T1POL: TP1_0, TP1_1 output Polarity control
0: Non-invert
1: Invert
This bit controls the polarity of the TP1_0 and TP1_1 output pins. When the bit is set
high the TM output pin will be inverted and not inverted when the bit is zero. It has no
effect if the TM is in the Timer/Counter Mode.
T1CAPTS: TM1 capture trigger source select
0: From TP1 pin
1: From TCK1 pin
T1CCLR: Select TM1 Counter clear condition
0: TM1 Comparator P match
1: TM1 Comparator A match
This bit is used to select the method which clears the counter. Remember that the
Standard TM contains two comparators, Comparator A and Comparator P, either of
which can be selected to clear the internal counter. With the T1CCLR bit set high,
the counter will be cleared when a compare match occurs from the Comparator A.
When the bit is low, the counter will be cleared when a compare match occurs from
the Comparator P or with a counter overflow. A counter overflow clearing method can
only be implemented if the CCRP bits are all cleared to zero. The T1CCLR bit is not
used in the PWM Mode, Single Pulse or Input Capture Mode.
TM1DL Register
Bit
7
6
5
4
3
2
1
0
Name
D7
D6
D5
D4
D3
D2
D1
D0
R/W
R
R
R
R
R
R
R
R
POR
0
0
0
0
0
0
0
0
Bit 7~0
TM1DL: TM1 Counter Low Byte Register bit 7 ~ bit 0
TM1 10-bit Counter bit 7 ~ bit 0
TM1DH Register
Bit
7
6
5
4
3
2
1
0
Name
—
—
—
—
—
—
D9
D8
R/W
—
—
—
—
—
—
R
R
POR
—
—
—
—
—
—
0
0
Bit 7~2
Bit 1~0
Unimplemented, read as "0"
TM1DH: TM1 Counter Low Byte Register bit 1 ~ bit 0
TM1 10-bit Counter bit 9 ~ bit 8
Rev. 1.20
82
December 14, 2016