HT45F4MA Datasheet, PDF (50/145 Pages) Holtek Semiconductor Inc – Power Bank Flash MCU

HT45F4MA/HT45FH4MA/HT45FH4MA-1
Power Bank Flash MCU
• CTRL Register
Bit
7
6
5
4
3
2
1
0
Name FSYSON —
—
—
—
LVRF
LRF
WRF
R/W
R/W
—
—
—
—
R/W
R/W
R/W
POR
0
—
—
—
—
x
0
0
Bit 7
Bit 6~3
Bit 2
Bit 1
Bit 0
FSYSON: fSYS Control in IDLE Mode
Describe elsewhere.
Unimplemented, read as "0"
LVRF: LVR function reset flag
0: Not occur
1: Occurred
This bit is set to 1 when a specific Low Voltage Reset situation condition occurs. This
bit can only be cleared to 0 by the application program.
LRF: LVR Control register software reset flag
0: Not occur
1: Occurred
This bit is set to 1 if the LVRC register contains any non defined LVR voltage register
values. This in effect acts like a software reset function. This bit can only be cleared to
0 by the application program.
WRF: WDT Control register software reset flag
Describe elsewhere.
Watchdog Time-out Reset During Normal Operation
The Watchdog time-out Reset during normal operation is the same as a LVR reset except that the
Watchdog time-out flag TO will be set to “1”.
W D T T im e - o u t
tR S T D + tS S T
In te rn a l R e s e t
Note: tRSTD is power-on delay, typical time=16.7ms
WDT Time-out Reset During Normal Operation Timing Chart
Watchdog Time-out Reset During SLEEP or IDLE Mode
The Watchdog time-out Reset during SLEEP or IDLE Mode is a little different from other kinds of reset.
Most of the conditions remain unchanged except that the Program Counter and the Stack Pointer will be
cleared to “0” and the TO flag will be set to “1”. Refer to the A.C. Characteristics for tSST details.
W D T T im e - o u t
tS S T
In te rn a l R e s e t
Note: The tSST is 15~16 clock cycles if the system clock source is provided by the HIRC.
The tSST is 1~2 clock for the LIRC.
WDT Time-out Reset During SLEEP or IDLE Timing Chart
Rev. 1.20
50
December 14, 2016