HT47C20L_05 Datasheet, PDF (8/45 Pages) Holtek Semiconductor Inc – R-F Type Low Voltage 8-Bit Mask MCU

HT47C20L
Program Memory - ROM
The program memory is used to store the program in-
structions which are to be executed. It also contains
data, table, and interrupt entries, and is organized into
2048´16 bits, addressed by the program counter and
table pointer.
Certain locations in the program memory are reserved
for special usage:
· Location 000H
This area is reserved for the initialization program. Af-
ter chip reset, the program always begins execution at
location 000H.
· Location 004H
This area is reserved for the external interrupt service
program. If the INT input pin is activated, and the inter-
rupt is enabled and the stack is not full, the program
begins execution at location 004H.
· Location 008H
This area is reserved for the time base interrupt ser-
vice program. If time base interrupt resulting from a
time base overflow, and if the interrupt is enabled and
the stack is not full, the program begins execution at
location 008H.
000H
D e v ic e in itia liz a tio n p r o g r a m
004H
E x te r n a l in te r r u p t s u b r o u tin e
008H
T im e B a s e In te r r u p t s u b r o u tin e
00C H
R e a l T im e C lo c k In te r r u p t s u b r o u tin e
010H
T im e r /e v e n t C o u n te r in te r r u p t s u b r o u tin e
P ro g ra m
ROM
n00H
L o o k - u p ta b le ( 2 5 6 w o r d s )
nFFH
L o o k - u p ta b le ( 2 5 6 w o r d s )
7FFH
1 6 b its
N o te : n ra n g e s fro m 0 to 7
Program Memory
· Location 00CH
This area is reserved for the real time clock interrupt
service program. If a real time clock interrupt occurs,
and if the interrupt is enabled and the stack is not full,
the program begins execution at location 00CH.
· Location 010H
This area is reserved for the timer/event counter inter-
rupt service program. If timer interrupt results from a
Timer/Event Counter A or B overflow, and if the inter-
rupt is enabled and the stack is not full, the program
begins execution at location 010H.
· Table location
Any location in the ROM space can be used as
look-up tables. The instructions ²TABRDC [m]² (the
current page, 1 page=256 words) and ²TABRDL [m]²
(the last page) transfer the contents of the lower-order
byte to the specified data memory, and the
higher-order byte to TBLH (08H). Only the destination
of the lower-order byte in the table is well-defined, the
higher-order byte of the table word are transferred to
the TBLH. The table higher-order byte register (TBLH)
is read only. The table pointer (TBLP) is a read/write
register (07H), which indicates the table location. Be-
fore accessing the table, the location must be placed
in TBLP. The TBLH is read only and cannot be re-
stored. If the main routine and the ISR (interrupt ser-
vice routine) both employ the table read instruction,
the contents of the TBLH in the main routine are likely
to be changed by the table read instruction used in the
ISR. Errors can occur. In other words using the table
read instruction in the main routine and the ISR simul-
taneously should be avoided. However, if the table
read instruction has to be applied in both the main rou-
tine and the ISR, the interrupt is supposed to be dis-
abled prior to the table read instruction. It will not be
enabled until the TBLH has been backed up. All table
related instructions need two cycles to complete the
operation. These areas may function as normal pro-
gram memory depending upon the requirements.
Stack Register - STACK
This is a special part of the memory which is used to
save the contents of the Program Counter only. The stack
is organized into four levels and is neither part of the
data nor part of the program space, and is neither read-
able nor writeable. The activated level is indexed by the
Table Location
Instruction(s)
*10
*9
*8
*7
*6
*5
*4
*3
*2
*1
*0
TABRDC [m] P10 P9
P8
@7 @6 @5 @4 @3 @2 @1 @0
TABRDL [m]
1
1
1
@7 @6 @5 @4 @3 @2 @1 @0
Table Location
Note: *10~*0: Bits of table location
P10~P8: Bits of current program counter
@7~@0: Bits of table pointer
Rev. 2.30
8
December 2, 2005