HT66F60A Datasheet, PDF (69/237 Pages) Holtek Semiconductor Inc – Enhanced A/D Flash Type 8-Bit MCU with EEPROM

HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
Under normal program operation, a Watchdog Timer time-out will initialise a device reset and set
the status bit TO. However, if the system is in the SLEEP or IDLE Mode, when a Watchdog Timer
time-out occurs, the TO bit in the status register will be set and only the Program Counter and Stack
Pointer will be reset. Three methods can be adopted to clear the contents of the Watchdog Timer.
The first is a WDT reset, which means a certain value except 01010B and 10101B written into the
WE4~WE0 field, the second is using the Watchdog Timer software clear instruction and the third is
via a HALT instruction.
There is only one method of using software instruction to clear the Watchdog Timer. That is to use
the single “CLR WDT” instruction to clear the WDT contents.
The maximum time out period is when the 2¹⁸ division ratio is selected. As an example, with a
32kHz LIRC oscillator as its source clock, this will give a maximum watchdog period of around 8
second for the 2¹⁸ division ratio, and a minimum timeout of 7.8ms for the 2⁸ division ration.
WDTC Register WE4~WE0 bits
“CLR WDT”Instruction
Reset MCU
CLR
LXT
LIRC
M
U
f_SUB
X
Low Speed Oscillator
Configuration option
f_S/2⁸
8-stage Divider
WDT Prescaler
WS2~WS0
(f_S/2⁸ ~ f_S/2¹⁸)
Watchdog Timer
8-to-1 MUX
WDT Time-out
(2⁸/f_S ~ 2¹⁸/f_S)
Rev. 1.00
69
March 20, 2013