HT66F60A Datasheet, PDF (58/237 Pages) Holtek Semiconductor Inc – Enhanced A/D Flash Type 8-Bit MCU with EEPROM

HT66F60A/HT66F70A
Enhanced A/D Flash Type 8-Bit MCU with EEPROM
Bit 2
bit 1
bit 0
HTO: High speed system oscillator ready flag
0: Not ready
1: Ready
This is the high speed system oscillator ready flag which indicates when the high speed
system oscillator is stable. This flag is cleared to “0” by hardware when the device is
powered on and then changes to a high level after the high speed system oscillator is
stable. Therefore this flag will always be read as “1” by the application program after
device power-on. The flag will be low when in the SLEEP or IDLE0 Mode but after
a wake-up has occurred, the flag will change to a high level after 1024 clock cycles
if the HXT oscillator is used or 15~16 clock cycles if the ERC or HIRC oscillator is
used.
IDLEN: IDLE Mode control
0: Disable
1: Enable
This is the IDLE Mode Control bit and determines what happens when the HALT
instruction is executed. If this bit is high, when a HALT instruction is executed the
device will enter the IDLE Mode. In the IDLE1 Mode the CPU will stop running
but the system clock will continue to keep the peripheral functions operational, if
FSYSON bit is high. If FSYSON bit is low, the CPU and the system clock will all stop
in IDLE0 mode. If the bit is low the device will enter the SLEEP Mode when a HALT
instruction is executed.
HLCLK: system clock selection
0: fH/2~fH/64 or fSUB
1: fH
This bit is used to select if the fH clock or the fH/2~fH/64 or fSUB clock is used as
the system clock. When the bit is high the fH clock will be selected and if low the
fH/2~fH/64 or fSUB clock will be selected. When system clock switches from the fH
clock to the fSUB clock and the fH clock will be automatically switched off to conserve
power.
Rev. 1.00
58
March 20, 2013