HT46RU26 Datasheet, PDF (66/86 Pages) Holtek Semiconductor Inc – A/D Type 8-Bit MCU with UART

HT46RU26/HT46CU26
Watchdog Timer
The Watchdog Timer is provided to prevent program mal-
functions or sequences from jumping to unknown loca-
tions, due to certain uncontrollable external events such
as electrical noise. It operates by providing a device reset
when the WDT counter overflows. The WDT clock is sup-
plied by one of two sources selected by configuration op-
tion: its own self contained dedicated internal WDT
oscillator or f_SYS/4. Note that if the WDT configuration op-
tion has been disabled, then any instruction relating to its
operation will result in no operation.
In the A/D Type series of microcontrollers, all Watchdog
Timer options, such as enable/disable, WDT clock
source and clear instruction type all selected through
configuration options. There are no internal registers as-
sociated with the WDT in the A/D Type MCU series. One
of the WDT clock sources is an internal oscillator which
has an approximate period of 65ms at a supply voltage
of 5V. However, it should be noted that this specified in-
ternal clock period can vary with VDD, temperature and
process variations. The other WDT clock source option
is the f_SYS/4 clock. Whether the WDT clock source is its
own internal WDT oscillator, RTC oscillator or from
f_SYS/4, it is further divided by 16 via an internal 15-bit
counter and a clearable single bit counter to give longer
Watchdog time-outs. As the clear instruction only resets
the last stage of the divider chain, for this reason the ac-
tual division ratio and corresponding Watchdog Timer
time-out can vary by a factor of two. The exact division
ratio depends upon the residual value in the Watchdog
Timer counter before the clear instruction is executed. It
is important to realise that as there are no independent
internal registers or configuration options associated
with the length of the Watchdog Timer time-out, it is
completely dependent upon the frequency of f_SYS/4,
RTC oscillator or the internal WDT oscillator.
If the f_SYS/4 clock is used as the WDT clock source, it
should be noted that when the system enters the Power
Down Mode, then the instruction clock is stopped and
the WDT will lose its protecting purposes. For systems
that operate in noisy environments, using the internal
WDT oscillator is strongly recommended.
Under normal program operation, a WDT time-out will
initialise a device reset and set the status bit TO. How-
ever, if the system is in the Power Down Mode, when a
WDT time-out occurs, the TO bit in the status register
will be set and only the Program Counter and Stack
Pointer will be reset. Three methods can be adopted to
clear the contents of the WDT. The first is an external
hardware reset, which means a low level on the RES
pin, the second is using the watchdog software instruc-
tions and the third is via a ²HALT² instruction.
There are two methods of using software instructions to
clear the Watchdog Timer, one of which must be chosen
by configuration option. The first option is to use the sin-
gle ²CLR WDT² instruction while the second is to use the
two commands ²CLR WDT1² and ²CLR WDT2². For the
first option, a simple execution of ²CLR WDT² will clear
the WDT while for the second option, both ²CLR WDT1²
and ²CLR WDT2² must both be executed to successfully
clear the WDT. Note that for this second option, if ²CLR
WDT1² is used to clear the WDT, successive executions
of this instruction will have no effect, only the execution of
a ²CLR WDT2² instruction will clear the WDT. Similarly
after the ²CLR WDT2² instruction has been executed,
only a successive ²CLR WDT1² instruction can clear the
Watchdog Timer.
Time Base
The internal time base function provides a periodic
time-out signal which in turn generates an interrupt. Its
time-out period ranges from 2¹²/f_S to 2¹⁵/f_S the actual
value is chosen via configuration option. When a time
base time-out occurs, the related interrupt request flags,
MFF in INTC1 and TBF in MFIC, are set. If the time base
interrupt enable bits, EMFI and ETBI, are enabled, and the
stack is not full, a subroutine call to location 18H will occur.
Note that as the TBF flag will not be cleared automatically,
it must be cleared manually by the application program.
Real Time Clock - RTC
The real time clock operates in a similar way to the time
base in that it is used to generate a regular interrupt sig-
nal. Its time-out period ranges from f_S/2⁸ to f_S/2¹⁵ the ac-
tual value is chosen by programming the RT0~RT2 bits in
the RTCC register. When an RTC time-out occurs, the re-
lated interrupt request flags, MFF in INTC1 and RTF in
MFIC, are set. If the interrupt enable bits, EMFI and ERTI,
are enabled, and the stack is not full, a subroutine call to
location 18H occurs. Note that as the RTF flag will not be
cleared automatically, it must be cleared manually by the
application program.
S y s te m C lo c k /4
R TC O S C 32768H z
W D T O S C 12kH z
R O M fs
C ode
O p tio n
D iv id e r
fs/2 ⁸
W D T P r e s c a le r
M a s k O p tio n
CK T
R
W D T C le a r
Watchdog Timer
CK T
R
T im e - o u t R e s e t
2 ^{1 5}/fS ~ 2 ^{1 6}/fS
2 ^{1 4}/fS ~ 2 ^{1 5}/fS
2 ^{1 3}/fS ~ 2 ^{1 4}/fS
2 ^{1 2}/fS ~ 2 ^{1 3}/fS
Rev. 1.00
66
June 12, 2008