HT46RU26 Datasheet, PDF (41/86 Pages) Holtek Semiconductor Inc – A/D Type 8-Bit MCU with UART

HT46RU26/HT46CU26
Note:
b7
b0
C K S M 1 M 0 S B E N M L S C S E N W C O L T R F S B C R R e g is te r
T r a n s m itt/R e c e iv e F la g
0 : N o t c o m p le te
1 : T r a n s m is s io n /r e c e p tio n c o m p le te
W r ite C o llis io n B it
0 : C o llis io n fr e e
1 : C o llis io n d e te c te d
S e le c tio n S ig n a l E n a b le /D is a b le B it
0 : S C S flo a tin g
1 : E n a b le
M S B /L S B F ir s t B it
0 : L S B s h ift fir s t
1 : M S B s h ift fir s t
S e r ia l B u s E n a b le /D is a b le B it
0 : D is a b le
1 : E n a b le
D e p e n d e n t u p o n C S E N b it
M a s te r /S la v e /B a u d R a te B its
M1 M0
0 0 M a s te r , b a u d r a te : fS IO
0 1 M a s te r , b a u d r a te : fS IO /4
1 0 M a s te r , b a u d r a te : fS IO /1 6
1 1 S la v e m o d e
C lo c k S o u r c e S e le c t B it
0 : fS IO = fS Y S /4
1 : fS IO = fS Y S
SPI Interface Control Register
The TRF flag will also generate an SPI interrupt signal, for more information refer to the Interrupt section.
w r ite to S B D R ( m a s te r )
S B E N = 1 , C S E N = 0 ( if p u ll- h ig h e d )
SCS
SBEN= CSEN= 1
SCK
SDI
D 7 /D 0 D 6 /D 1 D 5 /D 2 D 4 /D 3 D 3 /D 4 D 2 /D 5 D 1 /D 6 D 0 /D 7
SDO
D 7 /D 0 D 6 /D 1 D 5 /D 2 D 4 /D 3 D 3 /D 4 D 2 /D 5 D 1 /D 6 D 0 /D 7
SCK
SPI Bus Timing
SPI Operation
All communication is carried out using the 4-line inter-
face for both Master or Slave Mode. The timing diagram
shows the basic operation of the bus.
The CSEN bit in the SBCR register controls the overall
function of the SPI interface. Setting this bit high, will en-
able the SPI interface by allowing the SCS line to be ac-
tive, which can then be used to control the SPI interface.
If the CSEN bit is low, the SPI interface will be disabled
and the SCS line will be in a floating condition and can
therefore not be used for control of the SPI interface.
The SBEN bit in the SBCR register must also be high
which will place the SDI line in a floating condition and
the SDO line high. If in Master Mode the SCK line will be
either high or low depending upon the clock polarity con-
figuration option. If in Slave Mode the SCK line will be in
a floating condition. If SBEN is low then the bus will be
disabled and SCS, SDI, SDO and SCK will all be in a
floating condition.
In the Master Mode the Master will always generate the
clock signal. The clock and data transmission will be ini-
tiated after data has been written to the SBDR register.
In the Slave Mode, the clock signal will be received from
an external master device for both data transmission or
reception. The following sequences show the order to
be followed for data transfer in both Master and Slave
Mode:
· _{Master Mode:}
¨ _{Step 1}
Select the clock source using the CKS bit in the
SBCR control register
¨ _{Step 2}
Setup the M0 and M1 bits in the SBCR control regis-
ter to select the Master Mode and the required Baud
rate. Values of 00, 01 or 10 can be selected.
Rev. 1.00
41
June 12, 2008