BS66FV340 Datasheet, PDF (46/265 Pages) Holtek Semiconductor Inc – Enhanced Touch Voice A/D Flash MCU

BS66FV340/BS66FV350/BS66FV360
Enhanced Touch Voice A/D Flash MCU
• FC0 Register
Bit
Name
R/W
POR
7
CFWEN
R/W
0
6
FMOD2
R/W
1
5
FMOD1
R/W
1
4
FMOD0
R/W
1
3
FWPEN
R/W
0
2
FWT
R/W
0
1
FRDEN
R/W
0
0
FRD
R/W
0
Bit 7
Bit 6~4
Bit 3
Bit 2
Bit 1
Bit 0
CFWEN: Flash Memory Write enable control
0: Flash memory write function is disabled
1: Flash memory write function has been successfully enabled
When this bit is cleared to 0 by application program, the Flash memory write function
is disabled. Note that writing a "1" into this bit results in no action. This bit is used
to indicate that the Flash memory write function status. When this bit is set to 1 by
hardware, it means that the Flash memory write function is enabled successfully.
Otherwise, the Flash memory write function is disabled as the bit content is zero.
FMOD2~FMOD0: Mode selection
000: Write program memory
001: Block/Page erase program memory
010: Reserved
011: Read program memory
10x: Reserved
110: FWEN mode – Flash memory Write function Enabled mode
111: Reserved
When these bits are set to "001", the "Block erase" mode is selected for BS66FV340
while the "Page erase" mode is selected for BS66FV350/BS66FV360.
FWPEN: Flash memory Write Procedure Enable control
0: Disable
1: Enable
When this bit is set to 1 and the FMOD field is set to "110", the IAP controller will
execute the "Flash memory write function enable" procedure. Once the Flash memory
write function is successfully enabled, it is not necessary to set the FWPEN bit any
more.
FWT: Flash memory Write Initiate control
0: Do not initiate Flash memory write or Flash memory write process is completed
1: Initiate Flash memory write process
This bit is set by software and cleared by hardware when the Flash memory write
process is completed.
FRDEN: Flash memory Read Enable control
0: Flash memory read disable
1: Flash memory read enable
FRD: Flash memory Read Initiate control
0: Do not initiate Flash memory read or Flash memory read process is completed
1: Initiate Flash memory read process
This bit is set by software and cleared by hardware when the Flash memory read
process is completed.
• FC1 Register
Bit
7
6
5
4
3
2
1
0
Name
D7
D6
D5
D4
D3
D2
D1
D0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit 7~0
D7~D0: Whole chip reset pattern
When user writes a specific value of "55H" to this register, it will generate a reset
signal to reset whole chip.
Rev. 1.10
46
December 15, 2016