HT56R66_12 Datasheet, PDF (43/104 Pages) Holtek Semiconductor Inc – TinyPowerTM A/D Type with LCD 8-Bit OTP MCU

HT56R66/HT56R666
b7
TnM 1 TnM 0 TnS TnO N TnE
b0
T M R n C R e g is te r (n = 1 )
N o t im p le m e n te d , r e a d a s " 0 "
E v e n t C o u n te r a c tiv e e d g e s e le c t
1 : c o u n t o n fa llin g e d g e
0 : c o u n t o n r is in g e d g e
P u ls e W id th M e a s u r e m e n t a c tiv e e d g e s e le c t
1 : s ta r t c o u n tin g o n r is in g e d g e , s to p o n fa llin g e d g e
0 : s ta r t c o u n tin g o n fa llin g e d g e , s to p o n r is in g e d g e
T im e r /E v e n t C o u n te r c o u n tin g e n a b le
1 : e n a b le
0 : d is a b le
T im e r c lo c k s o u r c e
1 : fS U B (3 2 7 6 8 H z o r 3 2 K R C )
0 : fS Y S /4
O p e r a tin g m o d e s e le c t
TnM 1 TnM 0
0
0 ^{n o m o d e a v a ila b le}
0
1 e v e n t c o u n te r m o d e
1
0 tim e r m o d e
1
1 p u ls e w id th m e a s u r e m e n t m o d e
Timer/Event Counter Control Register - TMRnC
Configuring the Timer Mode
In this mode, the Timer/Event Counter can be utilised to
measure fixed time intervals, providing an internal inter-
rupt signal each time the Timer/Event Counter over-
flows. To operate in this mode, the Operating Mode
Select bit pair, TnM1/TnM0, in the Timer Control Regis-
ter must be set to the correct value as shown.
Control Register Operating Mode
Select Bits for the Timer Mode
Bit7 Bit6
10
In this mode the internal clock, fSYS , is used as the inter-
nal clock for 8-bit Timer/Event Counter 0 and f_SUB or
fSYS/4 is used as the internal clock for 16-bit Timer/Event
Counter 1. However, the clock source, fSYS, for the 8-bit
timer is further divided by a prescaler, the value of which
is determined by the Prescaler Rate Select bits
TnPSC2~TnPSC0, which are bits 2~0 in the Timer Con-
trol Register. After the other bits in the Timer Control
Register have been setup, the enable bit TnON or
TnON, which is bit 4 of the Timer Control Register, can
be set high to enable the Timer/Event Counter to run.
Each time an internal clock cycle occurs, the
Timer/Event Counter increments by one. When it is full
and overflows, an interrupt signal is generated and the
Timer/Event Counter will reload the value already
loaded into the preload register and continue counting.
The interrupt can be disabled by ensuring that the
Timer/Event Counter Interrupt Enable bit in the corre-
sponding Interrupt Control Register, is reset to zero.
P r e s c a le r O u tp u t
Configuring the Event Counter Mode
In this mode, a number of externally changing logic
events, occurring on the external timer pin, can be re-
corded by the Timer/Event Counter. To operate in this
mode, the Operating Mode Select bit pair, TnM1/TnM0,
in the Timer Control Register must be set to the correct
value as shown.
Control Register Operating Mode
Bit7 Bit6
Select Bits for the Event Counter Mode _{0 1}
In this mode, the external timer pin, is used as the
Timer/Event Counter clock source, however it is not di-
vided by the internal prescaler. After the other bits in the
Timer Control Register have been setup, the enable bit
TnON, which is bit 4 of the Timer Control Register, can
be set high to enable the Timer/Event Counter to run. If
the Active Edge Select bit, TnE, which is bit 3 of the
Timer Control Register, is low, the Timer/Event Counter
will increment each time the external timer pin receives
a low to high transition. If the Active Edge Select bit is
high, the counter will increment each time the external
timer pin receives a high to low transition. When it is full
and overflows, an interrupt signal is generated and the
Timer/Event Counter will reload the value already
loaded into the preload register and continue counting.
The interrupt can be disabled by ensuring that the
Timer/Event Counter Interrupt Enable bit in the corre-
sponding Interrupt Control Register, is reset to zero.
In c re m e n t
T im e r C o n tr o lle r
Rev. 1.40
T im e r + 1
T im e r + 2
Timer Mode Timing Chart
43
T im e r + N
T im e r + N + 1
May 11, 2012