BS83B08A-3 Datasheet, PDF (41/119 Pages) Holtek Semiconductor Inc – 8-Bit Touch Key Flash MCU

BS83B08A-3/BS83B12A-3/BS83B16A-3
BS83B08A-4/BS83B12A-4/BS83B16A-4
8-Bit Touch Key Flash MCU
NORMAL Mode to SLOW Mode Switching
When running in the NORMAL Mode, which uses the high speed system oscillator, and therefore
consumes more power, the system clock can switch to run in the SLOW Mode by setting the
HLCLK bit to “0” and setting the CKS2~CKS0 bits to “000” or “001” in the SMOD register.This
will then use the low speed system oscillator which will consume less power. Users may decide to
do this for certain operations which do not require high performance and can subsequently reduce
power consumption.
The SLOW Mode is sourced from the LIRC oscillator and therefore requires this oscillator to be
stable before full mode switching occurs. This is monitored using the LTO bit in the SMOD register.
SLOW Mode to NORMAL Mode Switching
In SLOW Mode the system uses LIRC low speed system oscillator. To switch back to the NORMAL
Mode, where the high speed system oscillator is used, the HLCLK bit should be set to “1” or
HLCLK bit is “0”, but CKS2~CKS0 is set to “010”, “011”, “100”, “101”, “110” or “111”. As a
certain amount of time will be required for the high frequency clock to stabilise, the status of the
HTO bit is checked. The amount of time required for high speed system oscillator stabilization
depends upon which high speed system oscillator type is used.
Entering the SLEEP Mode
There is only one way for the device to enter the SLEEP Mode and that is to execute the “HALT”
instruction in the application program with the IDLEN bit in SMOD register equal to “0”. When this
instruction is executed under the conditions described above, the following will occur:
• The system clock and Time Base clock will be stopped and the application program will stop at
the “HALT” instruction, but the fSUB clock will be on.
• The Data Memory contents and registers will maintain their present condition.
• The WDT will be cleared and resume counting.
• The I/O ports will maintain their present conditions.
• In the status register, the Power Down flag, PDF, will be set and the Watchdog time-out flag, TO,
will be cleared.
Entering the IDLE0 Mode
There is only one way for the device to enter the IDLE0 Mode and that is to execute the “HALT”
instruction in the application program with the IDLEN bit in SMOD register equal to “1” and the
FSYSON bit in CTRL register equal to “0”. When this instruction is executed under the conditions
described above, the following will occur:
• The system clock will be stopped and the application program will stop at the “HALT”
instruction, but the Time Base and the low frequency fSUB clock will be on.
• The Data Memory contents and registers will maintain their present condition.
• The WDT will be cleared and resume counting.
• The I/O ports will maintain their present conditions.
• In the status register, the Power Down flag, PDF, will be set and the Watchdog time-out flag, TO,
will be cleared.
Rev. 1.00
41
May 02, 2013