HT66FV130 Datasheet, PDF (156/259 Pages) Holtek Semiconductor Inc – Enhanced Voice Flash MCU

HT66FV130/HT66FV140
HT66FV150/HT66FV160
Enhanced Voice Flash MCU
Bit 5
Bit 4
Bit 3
Bit 2~0
ADCEN: A/D Converter function enable control
0: Disable
1: Enable
This bit controls the A/D internal function. This bit should be set to one to enable
the A/D converter. If the bit is set low, then the A/D converter will be switched
off reducing the device power consumption. When the A/D converter function is
disabled, the contents of the A/D data register pair, SADOH and SADOL, will be kept
unchanged.
ADRFS: A/D conversion data format select
0: A/D converter data format → SADOH = D [11:4]; SADOL = D [3:0]
1: A/D converter data format → SADOH = D [11:8]; SADOL = D [7:0]
This bit controls the format of the 12-bit converted A/D value in the two A/D data
registers. Details are provided in the A/D converter data register section.
Unimplemented, read as "0"
SACS2~SACS0: A/D converter external analog input channel select
000: AN0
001: Undefined
010: AN2
011: Undefined
100: Undefined
101: Undefined
110: AN6
111: AN7
SADC0 Register – HT66FV140/HT66FV150/HT66FV160
Bit
7
6
5
4
3
2
1
0
Name START ADBZ ADCEN ADRFS
—
SACS2 SACS1 SACS0
R/W
R/W
R
R/W
R/W
—
R/W
R/W
R/W
POR
0
0
0
0
—
0
0
0
Bit 7
Bit 6
Bit 5
Bit 4
START: Start the A/D Conversion
0→1→0: Start
This bit is used to initiate an A/D conversion process. The bit is normally low but if set
high and then cleared low again, the A/D converter will initiate a conversion process.
ADBZ: A/D Converter busy flag
0: No A/D conversion is in progress
1: A/D conversion is in progress
This read only flag is used to indicate whether the A/D conversion is in progress or
not. When the START bit is set from low to high and then to low again, the ADBZ flag
will be set to 1 to indicate that the A/D conversion is initiated. The ADBZ flag will be
cleared to 0 after the A/D conversion is complete.
ADCEN: A/D Converter function enable control
0: Disable
1: Enable
This bit controls the A/D internal function. This bit should be set to one to enable
the A/D converter. If the bit is set low, then the A/D converter will be switched
off reducing the device power consumption. When the A/D converter function is
disabled, the contents of the A/D data register pair, SADOH and SADOL, will be kept
unchanged.
ADRFS: A/D conversion data format select
0: A/D converter data format → SADOH = D [11:4]; SADOL = D [3:0]
1: A/D converter data format → SADOH = D [11:8]; SADOL = D [7:0]
This bit controls the format of the 12-bit converted A/D value in the two A/D data
registers. Details are provided in the A/D converter data register section.
Rev. 1.50
156
December 06, 2016