HT45R36 Datasheet, PDF (15/40 Pages) Holtek Semiconductor Inc – C/R to F Type 8-Bit OTP MCU

HT45R36
Timer/Event Counter
An 8-bit timer/event counter, known as Timer/Event
Counter, is implemented in the microcontroller. The
Timer/Event Counter contains an 8-bit programmable
count-up counter whose clock may come from an exter-
nal source or from the system clock. Using the external
clock input allows the user to count external events, mea-
sure time internals or pulse widths, or generate an accu-
rate time base. Using the internal clock allows the user to
generate an accurate time base.
There are 2 registers related to the Timer/Event Coun-
ter, TMR (0DH) and TMRC (0EH). Two physical regis-
ters are mapped to TMR location; writing to TMR places
the start value be placed in the Timer/Event Counter
preload register while reading TMR retrieves the con-
tents of the Timer/Event Counter. The TMRC is a
timer/event counter control register, which defines the
timer operating conditions.
The TM0, TM1 bits define the operating mode. The event
count mode is used to count external events, which
means the clock source comes from an external TMR
pin. The timer mode functions as a normal timer with the
clock source coming from the f_INT clock. The pulse width
measurement mode can be used to measure the high or
low level duration of an external signal on the TMR pin.
The counting is based on the f_INT clock source. In the
event counting or timer mode, once the timer/event coun-
ter starts counting, it will count from the current contents
in the Timer/Event Counter to FFH. Once overflow oc-
curs, the counter is reloaded from the Timer/Event Coun-
ter preload register and generates an interrupt request
flag (TF; bit 5 of INTC0) at the same time.
In the pulse width measurement mode, with the TON
and bits equal to one, once the TMR has received a
transient from low to high, or high to low if the bit is ²0², it
will start counting until the TMR pin returns to its original
level and resets the TON bit. The measured result will
remain in the Timer/Event Counter even if the activated
transient occurs again. In other words, only a single shot
measurement can be made. The TON bit must be set
again by software for further measurements to be made.
Note that, in this operating mode, the Timer/Event
Counter starts counting not according to the logic level
but according to the transient edges. In the case of
counter overflows, the counter is reloaded from the
Timer/Event Counter preload register and issues an in-
terrupt request just like the other two modes.
To enable the counting operation, the Timer ON bit,
TON; bit 4 of TMRC, should be set to ²1². In the pulse
width measurement mode, the TON will be cleared au-
tomatically after the measurement cycle is completed.
But in the other two modes the RCOCON can only be re-
set by instructions. The overflow of the Timer/Event
Counter is one of the wake-up sources. No matter what
the operation mode is, writing a 0 to ETI can disable the
interrupt service.
In the case of a Timer/Event Counter OFF condition,
writing data to the Timer/Event Counter preload register
will also reload that data to the Timer/Event Counter. But
if the Timer/Event Counter is already running, data writ-
ten to it will only be loaded into the Timer/Event Counter
preload register. The Timer/Event Counter will continue
to operate until an overflow occurs. When the
Timer/Event Counter is read, the clock will be blocked to
avoid errors. As clock blocking may results in a counting
error, this must be taken into consideration by the pro-
grammer. Bit0~Bit2 of the TMRC can be used to define
the pre-scaling stages of the internal clock sources of
Timer/Event Counter. The definitions are as shown.
Bit No.
0~2
3
4
5
6
7
Label
TPSC0~TPSC2
TE
TON
¾
TM0
TM1
Function
To define the prescaler stages, TPSC2, TPSC1, TPSC0=
000: f_INT=f_SYS
001: f_INT=f_SYS/2
010: f_INT=f_SYS/4
011: f_INT=f_SYS/8
100: f_INT=f_SYS/16
101: f_INT=f_SYS/32
110: f_INT=f_SYS/64
111: f_INT=f_SYS/128
To define the TMR active edge of the timer/event counter
(0=active on low to high; 1=active on high to low)
To enable or disable timer counting (0=disabled; 1=enabled)
Unused bit, read as ²0²
To define the operating mode, TM1, TM0=
01=Event count mode (external clock)
10=Timer mode (internal clock)
11=Pulse width measurement mode
00=Unused
TMRC (0EH) Register
Rev. 1.00
15
September 28, 2006