HT45R36 Datasheet, PDF (12/40 Pages) Holtek Semiconductor Inc – C/R to F Type 8-Bit OTP MCU

HT45R36
cillator is disabled, the WDT clock may still come from
the instruction clock and operate in the same manner
except that in the Power Down state the WDT will stop
counting and lose its protecting purpose. In this situation
the logic can only be restarted by external logic. The
high nibble and bit 3 of the WDTS can be used for user
defined flags.
If the device operates in a noisy environment, using the
internal WDT oscillator is the recommended choice,
since the HALT instruction will stop the system clock.
WS2 WS1 WS0
Division Ratio
0
0
0
1:1
0
0
1
1:2
0
1
0
1:4
0
1
1
1:8
1
0
0
1:16
1
0
1
1:32
1
1
0
1:64
1
1
1
1:128
WDTS (09H) Register
The WDT overflow under normal operation will generate
a ²chip reset² and set the status bit ²TO². But in the
Power Down mode, the overflow will generate a ²warm
reset², where only the Program Counter and SP are re-
set to zero. To clear the contents of the WDT, including
the WDT prescaler, three methods can be used; an ex-
ternal reset (a low level to RES), a software instruction
and a ²HALT² instruction. The software instruction in-
cludes ²CLR WDT² instruction and the instruction pair -
²CLR WDT1² and ²CLR WDT2². Of these two types of
instruction, only one can be active depending on the
configuration option - ²CLR WDT times selection op -
tion². If the ²CLR WDT² is selected, i.e. CLRWDT times
equal one, any execution of the ²CLR WDT² instruction
will clear the WDT. In the case that ²CLR WDT1² and
²CLR WDT2² are chosen, i.e. CLRWDT times equal
two, these two instructions must be executed to clear
the WDT; otherwise, the WDT may reset the chip as a
result of a time-out.
Power Down Operation - HALT
The Power Down mode is initialized by the ²HALT² in-
struction and results in the following...
· The system oscillator will be turned off but the WDT
oscillator keeps running, if the internal WDT oscillator
has been selected as the WDT source clock.
· The contents of the on chip RAM and registers remain
unchanged.
· The WDT and WDT prescaler will be cleared and will
resume counting, if the internal WDT oscillator has
been selected as the WDT source clock
· AlloftheI/Oportswillmaintaintheiroriginalstatus.
· The PDF flag is set and the TO flag is cleared.
The system can leave the Power Down mode by means
of an external reset, an interrupt, an external falling
edge signal on port A or a WDT overflow. An external re-
set causes a device initialisation and the WDT overflow
performs a ²warm reset². After the TO and PDF flags
are examined, the reason for chip reset can be deter-
mined. The PDF flag is cleared by a system power-up or
executing the ²CLR WDT² instruction and is set when
executing the ²HALT² instruction. The TO flag is set if a
WDT time-out occurs, and causes a wake-up that only
resets the program counter and SP; the other registers
maintain their their original status.
The port A and interrupt methods of wake-up can be
considered as a continuation of normal execution. Each
bit in port A can be independently selected by configura-
tion options to wake-up the device. When awakened
from an I/O port stimulus, the program will resume exe-
cution at the next instruction. If it is awakened due to an
interrupt, two sequences may happen. If the related in-
terrupt is disabled or the interrupt is enabled but the
stack is full, the program will resume execution at the
next instruction. If the interrupt is enabled and the stack
is not full, the regular interrupt response takes place. If
an interrupt request flag is set to ²1² before entering the
Power Down mode, the wake-up function of the related
interrupt will be disabled. Once a wake-up event occurs,
it takes 1024 t_SYS (system clock periods) to resume nor-
mal operation. In other words, a dummy period will be in-
serted after wake-up. If the wake-up results from an
interrupt acknowledgment, the actual interrupt subrou-
S y s te m C lo c k /4
W DT
O SC
O p tio n
S e le c t
8 - b it C o u n te r
W D T P r e s c a le r
7 - b it C o u n te r
8 -to -1 M U X
Watchdog Timer
W D T T im e - o u t
W S 0~W S 2
Rev. 1.00
12
September 28, 2006