HT45F5N Datasheet, PDF (124/202 Pages) Holtek Semiconductor Inc – Power Bank ASSP Flash MCU

HT45F5N/HT45FH5N
Power Bank ASSP Flash MCU
Protection and Inverting Control
Although a dead time has been inserted into the H.R_PWM complementary pair signals to prevent
excessive DC current, these two signals may also be in an inactive state resulting from some
unpredictable reasons, such as malfunctions or electrical noise. The device provides a protection
function to force the two signals to output inverting signals when the PWMnH or PWMnL signal is
in an inactive state. The inverting control circuitry determines whether the signals are inverted or not
using corresponding inverting control bit, OUTnHN or OUTnLN bit, in the OUTPC0 register.
OVP0I�T
UVP0I�T
OVP1I�T
UVP1I�T
OUVP0PC
OUVP1PC
OCPPC
P�otection
Ci�cuit
PWMnH
PWMnL
OUTnH�
OUTnL�
OUTnH
OUTnL
The device also includes over current protection, over voltage protection and under voltage
protection functions for the PWMn output signals which are described in the OCPn OCPPC register
and OUVPn section OUVPnPC register. The PWM output OUT0H/OUT0L, OUT1H/OUT1L can be
forced as inactive state controlled by OUT0HS/OUT0LS, OUT1HS/OUT1LS bits in the OUTPC0
register for either OCPn,OVPn or UVPn occurs. The OCPn/OVPn/UVPn also generates interrupt
to inform MCU. Once OCPn/OVPn/UVPn disappears, the OUT0H/OUT0L, OUT1H/OUT1L will
recover to send PWM output. Details about the current and voltage protection functions refer to the
"Over Current Protection" and "Over/Under Voltage Protection" chapters.
Programming Considerations
The following steps show the read and write procedures:
• Writing Data to DLLn/PWMnD
♦♦ Step 1. Write data to DLLn
––Note that here data is only written to the 4-bit buffer.
♦♦ Step 2. Write data to PWMnD
––Here data is written directly to PWMnD register and simultaneously data is latched from the
4-bit buffer to the DLLn register.
• Reading Data from DLLn/PWMnD
♦♦ Step 1. Read data from PWMnD
––Here data is read directly from the PWMnD register and simultaneously data is latched from
the DLLn register into the 4-bit buffer.
♦♦ Step 2. Read data from DLLn
––This step reads data from the 4-bit buffer.
Rev. 1.00
124
November 18, 2016