HT69F340 Datasheet, PDF (121/235 Pages) Holtek Semiconductor Inc – TinyPowerTM I/O Flash MCU with LCD & EEPROM

HT69F340/HT69F350/HT69F360
TinyPower^TM I/O Flash MCU with LCD & EEPROM
Bit 3
Bit 2
Bit 1
Bit 0
In the Compare Match Output Mode, the STIO1~STIO0 bits determine how the TM
output pin changes state when a compare match occurs from the Comparator A. The
TM output pin can be setup to switch high, switch low or to toggle its present state
when a compare match occurs from the Comparator A. When the STIO1~STIO0 bits
are both zero, then no change will take place on the output. The initial value of the TM
output pin should be setup using the STOC bit. Note that the output level requested by
the STIO1~STIO0 bits must be different from the initial value setup using the STOC
bit otherwise no change will occur on the TM output pin when a compare match
occurs. After the TM output pin changes state it can be reset to its initial level by
changing the level of the STON bit from low to high.
In the PWM Mode, the STIO1 and STIO0 bits determine how the TM output pin
changes state when a certain compare match condition occurs. The PWM output
function is modified by changing these two bits. It is necessary to change the values
of the STIO1 and STIO0 bits only after the TM has been switched off. Unpredictable
PWM outputs will occur if the STIO1 and STIO0 bits are changed when the TM is
running.
STOC: STM Output control bit
Compare Match Output Mode
0: Initial low
1: Initial high
PWM Mode/ Single Pulse Output Mode
0: Active low
1: Active high
This is the output control bit for the TM output pin. Its operation depends upon
whether TM is being used in the Compare Match Output Mode or in the PWM Mode/
Single Pulse Output Mode. It has no effect if the TM is in the Timer/Counter Mode. In
the Compare Match Output Mode it determines the logic level of the TM output pin
before a compare match occurs. In the PWM Mode it determines if the PWM signal is
active high or active low.
STPOL: STM Output polarity Control
0: Non-invert
1: Invert
This bit controls the polarity of the TM output pin. When the bit is set high the TM
output pin will be inverted and not inverted when the bit is zero. It has no effect if the
TM is in the Timer/Counter Mode.
STDPX: STM PWM period/duty Control
0: CCRP - period; CCRA - duty
1: CCRP - duty; CCRA - period
This bit, determines which of the CCRA and CCRP registers are used for period and
duty control of the PWM waveform.
STCCLR: Select STM Counter clear condition
0: TM Comparator P match
1: TM Comparator A match
This bit is used to select the method which clears the counter. Remember that the
Standard TM contains two comparators, Comparator A and Comparator P, either of
which can be selected to clear the internal counter. With the STCCLR bit set high,
the counter will be cleared when a compare match occurs from the Comparator A.
When the bit is low, the counter will be cleared when a compare match occurs from
the Comparator P or with a counter overflow. A counter overflow clearing method can
only be implemented if the CCRP bits are all cleared to zero. The STCCLR bit is not
used in the PWM, Single Pulse or Input Capture Mode.
Rev. 1.30
121
November 18, 2016