BC66F840 Datasheet, PDF (117/242 Pages) Holtek Semiconductor Inc – 2.4GHz Flash RF TX/RX MCU

BC66F840/BC66F850/BC66F860
2.4GHz Flash RF TX/RX MCU
Enhanced Type TM Operation Modes
The Enhanced Type TM can operate in one of five operating modes, Compare Match Output Mode,
PWM Output Mode, Single Pulse Output Mode, Capture Input Mode or Timer/Counter Mode. The
operating mode is selected using the TnAM1 and TnAM0 bits in the TMnC1, and the TnBM1 and
TnBM0 bits in the TMnC2 register.
ETM Operating Mode
CCRA Compare CCRA Timer/ CCRA PWM CCRA Single Pulse CCRA Input
Match Output Mode Counter Mode Output Mode Output Mode Capture Mode
CCRB Compare Match Output Mode
√
—
—
—
—
CCRB Timer/Counter Mode
—
√
—
—
—
CCRB PWM Output Mode
—
—
√
—
—
CCRB Single Pulse Output Mode
—
—
—
√
—
CCRB Input Capture Mode
—
—
—
—
√
“√”: permitted, “—”: not permitted
Compare Match Output Mode
To select this mode, bits TnAM1, TnAM0 and TnBM1, TnBM0 in the TMnC1/TMnC2 registers
should be all cleared to zero. In this mode once the counter is enabled and running it can be cleared
by three methods. These are a counter overflow, a compare match from Comparator A and a compare
match from Comparator P. When the TnCCLR bit is low, there are two ways in which the counter
can be cleared. One is when a compare match occurs from Comparator P, the other is when the
CCRP bits are all zero which allows the counter to overflow. Here both the TnAF and TnPF interrupt
request flags for Comparator A and Comparator P respectively, will both be generated.
If the TnCCLR bit in the TMnC1 register is high then the counter will be cleared when a compare
match occurs from Comparator A. However, here only the TnAF interrupt request flag will be
generated even if the value of the CCRP bits is less than that of the CCRA registers. Therefore when
TnCCLR is high no TnPF interrupt request flag will be generated.
As the name of the mode suggests, after a comparison is made, the TM output pin, will change
state. The TM output pin condition however only changes state when a TnAF or TnBF interrupt
request flag is generated after a compare match occurs from Comparator A or Comparator B. The
TnPF interrupt request flag, generated from a compare match from Comparator P, will have no
effect on the TM output pin. The way in which the TM output pin changes state is determined by the
condition of the TnAIO1 and TnAIO0 bits in the TMnC1 register for ETM CCRA, and the TnBIO1
and TnBIO0 bits in the TMnC2 register for ETM CCRB. The TM output pin can be selected using
the TnAIO1, TnAIO0 bits for the TPnA pin and TnBIO1, TnBIO0 bits for the TPnB pin to go high,
to go low or to toggle from its present condition when a compare match occurs from Comparator A
or a compare match occurs from Comparator B. The initial condition of the TM output pin, which
is setup after the TnON bit changes from low to high, is setup using the TnAOC or TnBOC bit for
TPnA or TPnB output pin. Note that if the TnAIO1, TnAIO0 and TnBIO1, TnBIO0 bits are zero
then no pin change will take place.
Rev. 1.40
117
May 24, 2017