HT82A525R_16 Datasheet, PDF (11/71 Pages) Holtek Semiconductor Inc – I/O Type USB 8-Bit OTP MCU with SPI

HT82A525R
I/O Type USB 8-Bit OTP MCU with SPI
System Architecture
A key factor in the high-performance features of the Holtek range of microcontrollers is attributed to
the internal system architecture. The range of devices take advantage of the usual features found
within RISC microcontrollers providing increased speed of operation and enhanced performance.
The pipelining scheme is implemented in such a way that instruction fetching and instruction
execution are overlapped, hence instructions are effectively executed in one cycle, with the exception
of branch or call instructions. An 8-bit wide ALU is used in practically all operations of the
instruction set. It carries out arithmetic operations, logic operations, rotation, increment, decrement,
branch decisions, etc. The internal data path is simplified by moving data through the Accumulator
and the ALU. Certain internal registers are implemented in the Data Memory and can be directly or
indirectly addressed. The simple addressing methods of these registers along with additional
architectural features ensure that a minimum of external components is required to provide a
functional I/O control system with maximum reliability and flexibility.
Clocking and Pipelining
The main system clock, derived from a Crystal oscillator is subdivided into four internally generated
non-overlapping clocks, T1~T4. The Program Counter is incremented at the beginning of the T1
clock during which time a new instruction is fetched. The remaining T2~T4 clocks carry out the
decoding and execution functions. In this way, one T1~T4 clock cycle forms one instruction cycle.
Although the fetching and execution of instructions takes place in consecutive instruction cycles, the
pipelining structure of the microcontroller ensures that instructions are effectively executed in one
instruction cycle. The exception to this are instructions where the contents of the Program Counter
are changed, such as subroutine calls or jumps, in which case the instruction will take one more
instruction cycle to execute.
For instructions involving branches, such as jump or call instructions, two machine cycles are
required to complete instruction execution. An extra cycle is required as the program takes one cycle
to first obtain the actual jump or call address and then another cycle to actually execute the branch.
The requirement for this extra cycle should be taken into account by programmers in timing sensitive
applications.
T1 T2 T3 T4 T1 T2 T3 T4 T1 T2 T3 T4
S y s te m C lo c k
O S C 2 ( R C o n ly )
PC
PC
PC +1
PC +2
F e tc h IN S T (P C )
E x e c u te IN S T (P C -1 )
F e tc h IN S T (P C + 1 )
E x e c u te IN S T (P C )
System Clocking and Pipelining
F e tc h IN S T (P C + 2 )
E x e c u te IN S T (P C + 1 )
1
M O V A ,[1 2 H ]
2
C A LL D E LA Y
3
C P L [1 2 H ]
4
:
5
:
6
NOP
D E LA Y :
F e tc h In s t. 1
E x e c u te In s t. 1
F e tc h In s t. 2
E x e c u te In s t. 2
F e tc h In s t. 3
F lu s h P ip e lin e
F e tc h In s t. 6
E x e c u te In s t. 6
F e tc h In s t. 7
Instruction Fetching
Rev. 1.80
11
March 11, 2016