HMC661LC4B Datasheet, PDF (7/14 Pages) Hittite Microwave Corporation – ULTRA-WIDEBAND 4 GS/s TRACK-AND-HOLD AMPLIFIER

HMC661LC4B
v00.0312
ULTRA-WIDEBAND 4 GS/s TRACK-AND-HOLD AMPLIFIER
DC - 18 GHz
Application Notes
General: The HMC661LC4B ultra-wideband single rank T/H amplifier is optimized for use in microwave data
conversion applications requiring maximum sampling bandwidth, high linearity over a very wide bandwidth, and
low noise. A key application of this device is front end sampling for high speed A/D converters to enhance their
input bandwidth and/or high frequency linearity. Although several high speed A/D converters offer enhanced
sample rates, few of them offer input bandwidth beyond a few GHz. In addition, maintenance of good sampling
linearity at frequencies beyond the UHF band is technologically challenging and most A/D converters suffer
rapidly degraded linearity above 1 or 2 GHz signal frequency. The HMC661LC4B can address these limitations
with its 18 GHz input bandwidth and excellent broadband linearity. Once sampling takes place within the T/H,
the low bandwidth held output waveform can be processed by an A/D with substantially reduced bandwidth. In
addition, A/D converter linearity performance limitations at high input frequencies are also mitigated because the
settled waveform is processed with the optimal baseband linearity of the A/D converter.
The single rank T/H has one T/H amplifier and produces an output which consists of two segments. In the track
mode interval of the output waveform (positive differential clock voltage) the device behaves as a unity gain
amplifier which replicates the input signal at the output subject to the input bandwidth and the output amplifier
bandwidth limitations. At the positive to negative clock transition the device samples the input signal with a
very narrow sampling time aperture and holds the output relatively constant during the negative clock interval
at a value which is representative of the signal at the instant of sampling. The single rank device (as opposed
to a dual rank T/H) is often preferable for front end sampling with A/D converters because most high-speed
A/Ds already have a T/H, usually with much less bandwidth, integrated at the front end of the converter. Hence,
the HMC661LC4B forms a composite dual rank assembly (or triple rank if there is a dual rank device in the
converter) with the T/H in the converter. For equal technologies and designs, a single rank device will usually have
better linearity and noise than a dual rank device, since the single rank has fewer stages. Hence, the single rank
device is often the optimum choice for front end sampling with high speed A/Ds.
ESD: On-chip ESD protection networks are incorporated on the terminals, but the RF/microwave compatible interfaces
provide minimal protection and ESD precautions should be used.
Power Supply Sequencing: The recommended power supply startup sequence is VccOB, VccOF, VccTH, VccCLK,
Vee / VeeCLK if biased from independent supplies. VccOB, VccOF, VccTH and VccCLK can be connected to one
+2 V supply if desired.
Input Signal Drive: For best results, the inputs should be driven differentially. The input can be driven single-ended
but the linearity of the device will be degraded somewhat. The unused input should be terminated in 50 Ohms
when driving the device single-ended.
Clock Input: The device is in track-mode when (CLKP – CLKN) is high and it is in hold-mode when (CLKP – CLKN)
is low. The clock inputs should be driven differentially if possible. The clock inputs can be driven single-ended
if desired but the single-ended amplitude/slew rate should be similar to the full differential amplitude / slew rate
recommended for differential drive. The unused input should be terminated in 50 Ohms.
The T/H-mode linearity of the device varies somewhat with clock power at lower clock frequencies as shown in
the performance data plots. This results from a weak dependence of the linearity on clock zero crossing slew rate
for slew rates beneath a critical value. For optimal linearity, a clock zero-crossing slew rate of roughly 2 - 4 V/ns
(per clock input) or more is recommended. For sinusoidal clock inputs, 4 V/ns corresponds to a sinusoidal clock
power per differential half-circuit input of -6 dBm at 4 GHz, 0 dBm at 2 GHz, and 6 dBm at 1 GHz. Regardless of
the clock frequency, a minimum clock amplitude of -6 dBm is recommended (per differential half-circuit input)..
Outputs: The outputs should be sensed differentially for the cleanest output waveforms. The output impedance is
50 Ohms resistive returned to the VccOB supply. The output stage is designed to drive 50 Ohms terminated to
ground on each differential half-circuit output. The device offers a true ground-referenced common mode output
that is usually within ±50 mV of ground; however it is possible to adjust the VccOB power supply slightly to fine
tune the output common-mode level to precisely 0 V if desired. Additionally, the common-mode output level may
be adjusted within the range of approximately ±0.5 V by adjusting the VccOB power supply according to the
approximate relation Vocm=(VccOB-2)/2 where Vocm is the output common mode voltage and VccOB can be
varied in the range of +1 V < VccOB < +3 V.
The bandwidth of the output amplifier that buffers the T/H signal between the hold-node and the 50 Ohm outputs
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