HMCAD1512 Datasheet, PDF (4/30 Pages) Hittite Microwave Corporation – Coarse and Fine Gain Control

HMCAD1512
v01.0812
8-BIT, DUAL-CHANNEL 450 MS/S OR
SINGLE-CHANNEL 900 MS/S A-TO-D CONVERTER
AC Specifications
AVDD = 1.8V, DVDD = 1.8V, OVDD = 1.8V, 50% clock duty cycle, -1 dBFS 71 MHz input signal, Gain = 1X, RSDS output data levels unless
otherwise noted
Parameter
Description
Min
Typ
Max
Unit
Analog Input
FPBW
Clock Inputs
F_Smax
Full Power Bandwidth
Max. Conversion Rate in Modes: Single Ch
Dual Ch
650
900 /450
MHz
MSPS
Min. Conversion Rate in Modes: Single Ch
F_smin
Dual Ch
120 /
60 /
MSPS
Digital and Switching Specifications
AVDD = 1.8V, DVDD = 1.8V, OVDD = 1.8V, RSDS output data levels, unless otherwise noted
Parameter
Description
Clock Inputs
DC
Duty Cycle
Compliance
LVDS supported up to 700 MHz
V_CK,sine
Differential input voltage swing, sine wave clock input
V_CK,CMOS
V_CM,CK
Voltage input range CMOS (CLKN connected to ground)
Input common mode voltage. Keep voltages within ground and
voltage of OVDD
C_CK
Differential Input capacitance
Logic inputs (CMOS)
V_HI
V_HI
V_LI
V_LI
I_HI
I_LI
C_I
Data Outputs
High Level Input Voltage. V_OVDD ≥ 3.0V
High Level Input Voltage. V_OVDD = 1.7V – 3.0V
Low Level Input Voltage. V_OVDD ≥ 3.0V
Low Level Input Voltage. V_OVDD = 1.7V – 3.0V
High Level Input leakage Current
Low Level Input leakage Current
Input Capacitance
Compliance
V_OUT
V_OUT
V_CM
Output coding
Differential output voltage, LVDS
Differential output voltage, RSDS
Output common mode voltage
Default/optional
Timing Characteristics
t_A
t_j
T_skew
T_SU
T_SLPCH
T_OVR
T_LATHSMD
T_LATHSMS
Aperture delay
Aperture jitter, One bit set to ‘1’ in jitter_ctrl<7:0>
Timing skew between ADC channels
Start up time from Power Down Mode and Deep Sleep Mode to
Active Mode in µs. See section “Clock Frequency” for details.
Start up time from Sleep Channel Mode to Active Mode
Out of range recovery time
Pipeline delay, Dual Channel Mode
Pipeline delay, Single Channel Mode
Min
Typ
Max
45
55
LVPECL, Sine wave, CMOS, LVDS
1500
V_OVDD
0.3
V_OVDD -0.3
3
2
0.8 ·V_OVDD
0
0.8
0
0.2 ·V_OVDD
+/-10
+/-10
3
LVDS / RSDS
350
150
1.2
Offset Binary/ 2’s complement
1.5
160
2.5
15
1
64
128
Unit
% high
mVpp
V
pF
V
V
V
V
µA
µA
pF
mV
mV
V
ns
fsrms
psrms
µs
µs
clock cycles
clock cycles
clock cycles
For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824
Phone: [phone] Fax: [phone] Order On-line at www.hittite.com
4
Application Support: Phone: [phone] or [e-mail]