HMC6000LP711E Datasheet, PDF (12/18 Pages) Hittite Microwave Corporation – Multi-Gbps Data Communications

HMC6000LP711E
v00.1112
Millimeterwave Transmitter
57 - 64 GHz
Theory of Operation
An integrated frequency synthesizer creates a low-phase noise LO between 16.3 and 18.3 GHz. The step size of the
synthesizer equates to 540MHz steps at RF when used with 308.5714 MHz reference crystal (compatible with the
IEEE channels of the ISM band) or 500 MHz steps if used with a 285.714 MHz reference crystal.
If the chip is configured for IQ baseband input, these signals are quatrature modulated onto an 8 to 9.1GHz sliding IF
using the synthesized LO divided by two. There are also options to input AM/FM/FSK/MSK waveforms directly to the
on-chip IF modulators. Contact Hittite application support for further guidance and application notes if interested in
these modes. The IF signal is then filtered and amplified with 17 dB of variable gain, then mixed with three times the
LO frequency to upconvert to an RF frequency between 57 and 64 GHz. Integrated notch filters attenuate the lower
mixing product at 40-46GHz. Two RF amplifier stages provide gain to allow up to 11 dBm differential output from the
IC to an integrated low profile antenna.
The phase noise and quadrature balance of the HMC6000LP711E is sufficient to carry up to 16QAM modulation for
high data rate operation..
There are no special power sequencing requirements for the HMC6000LP711E; all voltages are to be applied
simultaneously.
Register Array Assignments and Serial Interface
The register arrays for both the transmitter and receiver are organized into 16 rows of 8 bits. Using the serial interface,
the arrays are written or read one row at a time as shown in Figure 22 and Figure 23, respectively. Figure 22 shows
the sequence of signals on the ENABLE, CLK, and DATA lines to write one 8-bit row of the register array. The ENABLE
line goes low, the first of 18 data bits (bit 0) is placed on the DATA line, and 2 ns or more after the DATA line stabilizes,
the CLK line goes high to clock in data bit 0. The DATA line should remain stable for at least 2 ns after the rising edge
of CLK.
The Tx IC will support a serial interface running up to several hundred MHz, and the interface is 1.2V CMOS levels.
A write operation requires 18 data bits and 18 clock pulses, as shown in Figure 23. The 18 data bits contain the 8-bit
register array row data (LSB is clocked in first), followed by the register array row address (ROW0 through ROW15,
000000 to 001111, LSB first), the Read/Write bit (set to 1 to write), and finally the Tx chip address 110, LSB first).
Note that the register array row address is 6 bits, but only four are used to designate 16 rows, the two MSBs are 0.
After the 18th clock pulse of the write operation, the ENABLE line returns high to load the register array on the IC; prior
to the rising edge of the ENABLE line, no data is written to the array. The CLK line should have stabilized in the low
state at least 2 ns prior to the rising edge of the ENABLE line.
Figure 22. Timing Diagram for writing a row of the Transmitter Serial Interface
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