HN58X24128I Datasheet, PDF (8/22 Pages) Hitachi Semiconductor – Two-wire serial interface, 128k EEPROM (16-kword x 8-bit), 256k EEPROM (32-kword x 8-bit)

HN58X24128I/HN58X24256I
Device Address (A0, A1, A2)
Eight devices can be wired for one common data bus line as maximum. Device address pins are used to
distinguish each device and device address pins should be connected to V_CC or V_SS. When device address
code provided from SDA pin matches corresponding hard-wired device address pins A0 to A2, that one
device can be activated.
Pin Connections for A0 to A2
Pin connection
Max connect
Memory size number
A2
A1
A0
Note
128k bit
8
V_CC/V_SS*¹ V_CC/V_SS V_CC/V_SS
256k bit
8
V_CC/V_SS V_CC/V_SS V_CC/V_SS
Note: 1. “V_CC/V_SS” means that device address pin should be connected to V_CC or V_SS.
Write Protect (WP)
When the Write Protect pin (WP) is high, the write protection feature is enabled and operates as shown in
the following table. When the WP is low, write operation for all memory arrays are allowed. The read
operation is always activated irrespective of the WP pin status. WP should be fixed high or low during
operations since WP does not provide a latch function.
Write Protect Area
Write protect area
WP pin status 128k bit
V_IH
Upper 1/8 (16k bit)
V_IL
Normal read/write operation
256k bit
Upper 1/8 (32k bit)
8