HD74LV166A Datasheet, PDF (8/16 Pages) Hitachi Semiconductor – Parallel-Load 8-bit Shift Register

HD74LV166A
Switching Characteristics
• V_CC = 2.5 ± 0.2 V
Ta = 25°C
Item
Maximum
clock
frequency
Propa-
gation
delay time
Setup time
Hold time
Pulse
width
Symbol
fmax
t_PLH/t_PHL
t_PHL
t_su
t_h
t_w
Min
50
40
—
—
—
—
7.0
6.5
7.0
8.5
–0.5
–0.5
–0.5
8.0
8.5
Typ Max
80 —
65 —
12.2 19.8
15.3 23.3
10.8 16.0
14.2 19.5
——
——
——
——
——
——
——
——
——
Ta = –40 to 85°C
Min
Max
45
—
35
—
1.0
22.0
1.0
26.0
1.0
18.0
1.0
22.0
7.0
—
8.5
—
8.5
—
9.5
—
0.0
—
0.0
—
0.0
—
9.0
—
9.0
—
Unit
MHz
ns
ns
ns
ns
ns
Test
Conditions
C_L = 15 pF
C_L = 50 pF
C_L = 15 pF
C_L = 50 pF
C_L = 15 pF
C_L = 50 pF
FROM
(Input)
TO
(Output)
CLK
Q_H
CLR
CLK INH before CLK ↑
Data before CLK ↑
SH/LD high before CLK ↑
SER before CLK ↑
PAR data after SH/LD ↑
SER data after CLK ↑
SH/LD high after CLK ↑
CLR low
CLK H or L
8