HD74LV166A Datasheet, PDF (2/16 Pages) Hitachi Semiconductor – Parallel-Load 8-bit Shift Register

HD74LV166A
Function Table
Inputs
Internal outputs
CLR
SH/LD CLK INH CLK
SER
A ... H
QA
QB
L
X
X
X
X
X
L
L
H
X
L
L
X
X
Q_A0
Q_B0
H
L
L
↑
X
a ... h
a
b
H
H
H
Note:
H
L
↑
H
X
H
Q_An
H
L
↑
L
X
L
Q_An
X
H
↑
X
X
Q_A0
Q_B0
H: High level
L: Low level
↑: Low to high transition
X: Immaterial
a ... h: Parallel data
Q_A0 ... Q_H0: Outputs remain unchanged.
Q_An ... Q_Gn: Data shifted from the previous stage on a positive edge at the clock input.
Output
QH
L
Q_H0
h
Q_Gn
Q_Gn
Q_H0
Pin Arrangement
SER 1
A2
B3
C4
D5
CLK INH 6
CLK 7
GND 8
(Top view)
16 V_CC
15 SH/LD
14 H
13 QH
12 G
11 F
10 E
9 CLR
2