HA16117F Datasheet, PDF (7/31 Pages) Hitachi Semiconductor – CMOS Watchdog Timer

HA16117F Series
Internal Operation and Usage Notes
Figure 3 shows an equivalent circuit of the watchdog timer block with a V_CC pin level of 5 V and ACC pin
level of 0 V, and the following pages show internal operation timing charts for different P-RUN
frequencies. (Descriptions apply to conditions C_F = 0.01 µF, C_R = 0.1 µF, R₂/(R₁ + R₂) = 0.6.)
Operation
The power-on and auto-reset circuit is a multivibrator with timing controlled by C_R charge current I₁ and
discharge current I₂. As I₁ : I₂ ≈ 3 : 1 (Typ design value), when the (WD) (watchdog filter circuit output)
on-duty is 25% or above, the C_R pin potential does not fall below 1.6 V. Therefore, (C) in the figure below
is fixed low, and RES is not output. The (WD) on-duty varies according to the P-RUN frequency. If the
frequency is lower or higher than the design value, the (WD) on-duty decreases, and at 25% or below, RES
is output. Refer to the timing charts on the following pages for an explanation of the operation of the
watchdog filter.
Usage Notes
• When the P-RUN frequency reaches 20 kHz or above, t_OFF is short (see the timing charts on the
following pages). This must be borne in mind in the design stage.
• If the P-RUN frequency fluctuates, RES may also be output within the normal detection set frequency
(see the timing charts on the following pages).
• Detection frequencies f_H and f_L described in the Data Book are Typ values, and a certain amount of
dispersion can be expected. A margin of ±30% or more should be allowed for in the design.
I_w
0.8 µ
typ
C_F
0.01 µ
P-RUN
A
V_CC (5 V)
3.6 V
−
+
Q
0.9 V ^−
+
WD
DQ
φ_Q
1/2
Q
frequency divider
Watchdog filter circuit
0.1 µ
C_R
I₁
8 µ typ
3.2 V
1.6 V
I₂
B
10.7 µ
typ
Low voltage detection block
−
C
+
RES
Power-on and auto-reset circuit
Figure 3 Watchdog Timer Evaliation Circuit
7