HA16117F Datasheet, PDF (26/31 Pages) Hitachi Semiconductor – CMOS Watchdog Timer

HA16117F Series
Reset High Time vs. K (Tadj Constant)
100 m
10 m
0.56 0.6
0.7
Tadj constant K
R₁
V_CC
Tadj
R₂
5V
P-RUN ACC
0.01 µ
C_F
C_R
0.1 µ
GND
RES
0.8
Oscilloscope
Test circuit
K = ^R2
R₁ + R₂
Duty-cycle dependence of
P-RUN normal frequency range
1M
MPU system abnormal
100 k
Abnormal if duty
cycle is 0%
10 k
1 k ^{MPU system normal}
Abnormal if duty
cycle is 100%
100
Pulse
generator
5V
0V
0.01 µ
5V
V_CC
Tadj
P-RUN ACC
C_F
C_R
0.1 µ
GND
RES
510 R
750 R
Oscilloscope
10
MPU system abnormal
1
0
50
100
P-RUN input pulse duty cycle (%)
Test circuit
Notes: 1. Normal detection is assumed when RES is not output.
2. The figure at left is for a constant P-RUN frequency.
See "8. Summary of cases where P-RUN frequency
fluctuates" for cases where the frequency fluctuates.
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