HD74LV126A Datasheet, PDF (6/14 Pages) Hitachi Semiconductor – Quad. Bus Buffer Gates with 3-state Outputs

HD74LV126A
Switching Characteristics
• V_CC = 2.5 ± 0.2 V
Ta = 25°C
Ta = –40 to 85°C
Item
Propa-
gation
delay
time
Enable
time
Symbol Min Typ
t_PLH
— 7.1
t_PHL
— 9.2
t_ZH
— 7.4
t_ZL
Max Min
13.0 1.0
16.5 1.0
13.0 1.0
Disable t_HZ
time
t_LZ
— 9.5 16.5 1.0
— 5.7 14.7 1.0
— 8.1 18.2 1.0
Max
15.5
18.5
15.5
18.5
17.0
20.5
Unit Test Conditions
ns
C_L = 15 pF
C_L = 50 pF
ns
C_L = 15 pF
C_L = 50 pF
ns
C_L = 15 pF
C_L = 50 pF
• V_CC = 3.3 ± 0.3 V
Ta = 25°C
Ta = –40 to 85°C
Item
Propa-
gation
delay
time
Enable
time
Symbol Min Typ
t_PLH
— 5.0
t_PHL
— 6.4
t_ZH
— 5.1
t_ZL
Max Min
8.0 1.0
11.5 1.0
8.0 1.0
Disable t_HZ
time
t_LZ
— 6.6 11.5 1.0
— 4.4 9.7 1.0
— 6.1 13.2 1.0
Max
9.5
13.0
9.5
13.0
11.5
15.0
Unit Test Conditions
ns
C_L = 15 pF
C_L = 50 pF
ns
C_L = 15 pF
C_L = 50 pF
ns
C_L = 15 pF
C_L = 50 pF
FROM
(Input)
A
TO
(Output)
Y
OE
Y
OE
Y
FROM
(Input)
A
TO
(Output)
Y
OE
Y
OE
Y
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