HD74LV126A Datasheet, PDF (10/14 Pages) Hitachi Semiconductor – Quad. Bus Buffer Gates with 3-state Outputs

HD74LV126A
• Waveform-1
Input A
tr
10 %
90 %
50 %V_CC
t_PLH
tf
90 %
50 %V_CC
10 %
t_PHL
Output Y
50 %V_CC
50 %V_CC
V_CC
GND
V_OH
V_OL
• Waveform-2
Input OE
Waveform - A
Waveform - B
tr
10 %
90 %
50 %V_CC
t_ZL
tf
90 %
50 %V_CC
10 %
t_LZ
50 %V_CC
t_ZH
t_HZ
50 %V_CC
V_OL + 0.3 V
V_OH – 0.3 V
V_CC
GND
V_CC
V_OL
V_OH
GND
Notes:
1. t_r ≤ 3 ns, t_f ≤ 3 ns
2. Input waveform: PRR ≤ 1 MHz, duty cycle 50%
3. Waveform-A is for an output with internal conditions such that the output is low except when
disabled by the output control.
4. Waveform-B is for an output with internal conditions such that the output is high except when
disabled by the output control.
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