HD404654 Datasheet, PDF (57/109 Pages) Hitachi Semiconductor – 4-Bit Single-Chip Microcomputer

HD404654 Series
Input capture
Input capture
status flag (ICSF) error flag (ICEF)
Error
control
logic
Timer D interrupt
request flag (IFTD)
EVND
Edge
detection
logic
Timer read
register DU
(TRDU)
Timer read
register DL
(TRDL)
Read signal
Clock
Input capture
timer control
Timer counter D
(TCD)
Overflow
Selector
3
Timer mode
register D1
(TMD1)
System
clock
ø_PER
Prescaler S (PSS)
Edge detection control
Timer mode
register D2
(TMD2)
2
Edge detection
selection register
2 (ESR2)
Figure 43 (B) Block Diagram of Timer D (in Input Capture Timer Mode)
Timer D Operations:
• Free-running/reload timer operation: The free-running/reload operation, input clock source, and
prescaler division ratio are selected by timer mode register D1 (TMD1: $010).
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