HD74CDC2510B Datasheet, PDF (5/11 Pages) Hitachi Semiconductor – 3.3-V Phase-lock Loop Clock Driver

HD74CDC2510B
Pin Function
Pin name
CLK
FBIN
G
FBOUT
1Y(0:9)
AV_CC
AGND
V_CC
GND
No.
Type Description
24
I
Clock input. CLK provides the clock signal to be distributed by the
HD74CDC2510B clock driver. CLK is used to provide the
reference signal to the integrated PLL that generates the clock
output signals. CLK must have a fixed frequency and fixed phase
for the PLL to obtain phase lock. Once the circuit is powered up
and a valid CLK signal is applied, a stabilization time is required for
the PLL to phase lock the feedback signal to its reference signal.
13
I
Feedback input. FBIN provides the feedback signal to the internal
PLL. FBIN must be hard-wired to FBOUT to complete the PLL. The
integrated PLL synchronizes CLK and FBIN so that there is
nominally zero phase error between CLK and FBIN.
11
I
Output bank enable. G is the output enable for outputs 1Y(0:9).
When G is low, outputs 1Y(0:9)are disabled to a logic-low state.
When G is high, all outputs 1Y(0:9) are enabled and switch at the
same frequency as CLK.
12
O
Feedback output. FBOUT is dedicated for external feedback. It
switches at the same frequency as CLK. When externally wired to
FBIN, FBOUT completes the feedback loop of the PLL.
3, 4, 5, 8, 9, O
15, 16, 17,
20, 21
Clock outputs. These outputs provide low-skew copies of CLK.
Output bank 1Y(0:9) is enabled via the G input. These outputs can
be disabled to a logic low state by deasserting the G control input.
23
Power Analog power supply. AV_CC provides the power reference for the
analog circuitry. In addition, AV_CC can be used to bypass the PLL
for test purposes. When AV_CC is strapped to ground, PLL is
bypassed and CLK is buffered directly to the device outputs.
1
Ground Analog ground. AGND provides the ground reference for the
analog circuitry.
2, 10, 14, 22 Power Power supply
6, 7, 18,19 Ground Ground
5