HD74CDC2510B Datasheet, PDF (1/11 Pages) Hitachi Semiconductor – 3.3-V Phase-lock Loop Clock Driver

HD74CDC2510B
3.3-V Phase-lock Loop Clock Driver
ADE-205-219F (Z)
7th. Edition
October 1999
Description
The HD74CDC2510B is a high-performance, low-skew, low-jitter, phase-lock loop clock driver. It uses a
phase-lock loop (PLL) to precisely align, in both frequency and phase, the feedback (FBOUT) output to the
clock (CLK) input signal. It is specifically designed for use with synchronous DRAMs. The
HD74CDC2510B operates at 3.3 V V_CC and is designed to drive up to five clock loads per output.
Bank of outputs provide ten low-skew, low-jitter copies of the input clock. Output signal duty cycles are
adjusted to 50 percent independent of the duty cycle at the input clock. Bank of outputs can be enabled or
disabled via the control (G) inputs. When the G inputs are high, the outputs switch in phase and frequency
with CLK; when the G inputs are low, the outputs are disabled to the logic-low state.
Unlike many products containing PLLs, the HD74CDC2510B does not require external RC networks. The
loop filter for the PLL is included on-chip, minimizing component count, board space, and cost.
Because it is based on PLL circuitry, HD74CDC2510B requires a stabilization time to achieve phase lock
of the feedback signal to the reference signal. This stabilization time is required, following power up and
application of a fixed-frequency, fixed-phase signal at CLK, as well as following any changes to the PLL
reference or feedback signals. The PLL can be bypassed for test purposes by strapping AV_CC to ground.
Features
• Meets “PC SDRAM registered DIMM design support document, Rev. 1.2”
• Phase-lock loop clock distribution for synchronous DRAM applications
• External feedback (FBIN) pin is used to synchronize the outputs to the clock input
• No external RC network required
• Support spread spectrum clock (SSC) synthesizers
Note: Only by a change of a suffix (A to B) for standardization, there isn’t any change of the product.