HD66206 Datasheet, PDF (5/21 Pages) Hitachi Semiconductor – 80-Channel Column/Common Driver for Middle- or Large-sized Liquid Crystal Panel

HD66206
Block Functions
Liquid crystal display drive circuit
Generates one of four levels V1 to V4 to the output pin to drive the liquid crystal display according to the
combination of data of the 80-bit latch circuit and the M signal.
80-bit latch circuit
Latches data of the 80-bit bi-directional shift register (also used as a latch circuit) at the falling edge of
CL1, and transmits it to the liquid crystal display drive circuit.
80-bit bi-directional shift register (also used as a latch circuit)
When FCS is low, this register functions as an 80-bit shift register. At this time, D0L and D1R are used
as data input/output pins. When FCS is high, this register functions as a 20 × 4-bit unit latch circuit. At
this time, data that is input in parallel to data input pin D0L, D1R, D2 and D3 is converted to 4-bit data,
and then is latched to this register according to the latch signal generated by the selector.
Data conversion circuit
When FCS is low, D0L and D1R are used as data input/output pins. When FCS is high, D0L, D1R, D2,
and D3 are input data.
Selector
Decodes output data from the counter and generates a latch signal. Functions when latching data at
serial-latch operation (when FCS is high). At this time, after 80 bits of data Y1 to Y80 are completely
latched, the operation of the selector terminates. Even if input data changes, data in the latch circuit is
maintained.
Operating mode switching circuit
Switches common driver operation (when FCS is low) and column driver operation (when FCS is high).
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