2SK1831 Datasheet, PDF (4/6 Pages) Hitachi Semiconductor – Silicon N-Channel MOS FET

2SK1831, 2SK1832
Power vs. Temperature Derating
75
50
25
0
50
100
150
Case Temperature Tc (°C)
Maximum Safe Operation Area
50
30
µ
10
PW
3
1
0.3
OabrypeRear_Dais_Stiloim(noinitne)^D_dt^Chi^Os^{perat=ion10(Tm}_c ^s₌⁽₂¹₅^s_°C^ho₎ ^t)
Ta = 25°C
0.1
0.05
K1831
K1832
1 3 10 30 100 300
1000
Drain to Source Voltage V_DS (V)
Normalized Transient Thermal Impedance vs. Pulse Width
3
1 ^D=1
0.5
0.3 _0.2
0.1 ^0.1
0.05
θch – c(t) = γ s(t).θch – c
θch – c = 2.50°C/W, Tc = 25°C
P_DM
0.03
0.01
0.02
0.01 _{1 Shot Pulse}
PW
T
D
=
PW
T
10 µ
100 µ
1m
10 m
100 m
1
10
Pulse Width PW (S)
4