HM5264165F-75 Datasheet, PDF (31/67 Pages) Hitachi Semiconductor – 64M LVTTL interface SDRAM 133 MHz/100 MHz

HM5264165F/HM5264805F/HM5264405F-75/A60/B60
Write command to Read command interval:
1. Same bank, same ROW address: When the read command is executed at the same ROW address of the
same bank as the preceding write command, the read command can be performed after an interval of no less
than 1 clock. However, in the case of a burst write, data will continue to be written until one cycle before the
read command is executed.
WRITE to READ Command Interval (1)
CLK
Command
DQM,
DQMU/DQML
Din
Dout
WRIT READ
in A0
Column = A
Write _{Column = B}
Read
WRITE to READ Command Interval (2)
out B0 out B1
CAS Latency
Column = B
Dout
out B2
out B3
Burst Write Mode
CAS Latency = 2
Burst Length = 4
Bank 0
CLK
Command
DQM,
DQMU/DQML
Din
WRIT
READ
in A0
in A1
Dout
Column = A
Write
Column = B
Read
out B0 out B1
CAS Latency
Column = B
Dout
out B2
out B3
Burst Write Mode
CAS Latency = 2
Burst Length = 4
Bank 0
2. Same bank, different ROW address: When the ROW address changes, consecutive read commands
cannot be executed; it is necessary to separate the two commands with a precharge command and a bank-
active command.
3. Different bank: When the bank changes, the read command can be performed after an interval of no less
than 1 clock, provided that the other bank is in the bank-active state. However, in the case of a burst write,
data will continue to be written until one clock before the read command is executed (as in the case of the
same bank and the same address).
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