HM5264165F-75 Datasheet, PDF (30/67 Pages) Hitachi Semiconductor – 64M LVTTL interface SDRAM 133 MHz/100 MHz

HM5264165F/HM5264805F/HM5264405F-75/A60/B60
Read command to Write command interval:
1. Same bank, same ROW address: When the write command is executed at the same ROW address of the
same bank as the preceding read command, the write command can be performed after an interval of no less
than 1 clock. However, DQM, DQMU/DQML must be set High so that the output buffer becomes High-Z
before data input.
READ to WRITE Command Interval (1)
CLK
Command
DQM, CL=2
DQMU
/DQML _CL=3
Din
Dout
READ WRIT
in B0 in B1 in B2 in B3
High-Z
READ to WRITE Command Interval (2)
Burst Length = 4
Burst write
CLK
Command
DQM,
DQMU/DQML
Dout
CL=2
CL=3
Din
READ
WRIT
2 clock
High-Z
High-Z
2. Same bank, different ROW address: When the ROW address changes, consecutive write commands
cannot be executed; it is necessary to separate the two commands with a precharge command and a bank-
active command.
3. Different bank: When the bank changes, the write command can be performed after an interval of no less
than 1 clock, provided that the other bank is in the bank-active state. However, DQM, DQMU/DQML must
be set High so that the output buffer becomes High-Z before data input.
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