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HD74AC283 Datasheet, PDF (3/12 Pages) Hitachi Semiconductor – 4-bit Binary Full Adder with Fast Carry
HD74AC283/HD74ACT283
stage. Figure d shows a method of implementing a 5-input encoder, where the inputs are equally weighted.
The outputs S0, S1 and S2 present a binary number equal to the number of inputs I1 – I5 that are true. Figure
e shows one method of implementing a 5-input majority gate. When three or more of the inputs I1 – I5 are
true, the output M5 is true.
Fig. a Active HIGH varsus Active LOW Interpretation
Logic levels
C0
A0
A1
A2
A3 B0
B1
B2
B3
S0
S1
S2
S3
C4
L L H L HH L L H H H L L H
Active HIGH
0 0 1 0 11 0 0 1 1 1 0 0 1
Active LOW
1 1 0 1 00 1 1 0 0 0 1 1 0
Active HIGH: 0 + 10 + 9 = 3 + 16
Active LOW: 1 + 5 + 6 = 12 + 0
L
A0 B0 A1 B1 A2 B2 A3 B3
C0
C4
S0
S1
S2
S3
C3
Fig. b 3-bit Adder
A0 B0 A1 B1
C10
A10 B10
A0 B0 A1 B1
A2 B2 A3 B3
C0
C0
C4
C11
S0
S1
S2
S3
S0
S1
C2
S10
Fig. c 2-bit and 1-bit adders
3