HD49815TF Datasheet, PDF (18/25 Pages) Hitachi Semiconductor – Digital Camera Signal Processor

HD49815TF
c. TG and SSG
The TG generates the signals required to drive the CCD sensor (H1, H2, RG, SG1/2, and the V
transfer pulse), and the CDS/AGC control signals (SP1 and SP2).
In addition, the SSG generates the signals to synchronize with the TV monitor (the Sync signal).
The drive timing of the generated signals differs according to the manufacturer and the
specifications of the CCD sensor. Setting the state data enables setting of any timing.
The state data of TG and SSG can be set in TM_A0, A1, A2, A3, and A8.
d. AWB- and AE-detection blocks
The HD49815TF provides automatic white-balance (AWB) and automatic-iris (AE) detection
circuits that are indispensable for a camera.
The AWB-detection block takes the R-Y and B-Y color-difference signals completed the color-
signal processing, and converts to the R-B and MG-G axes. The converted signals are sent to
circuits for the white detection to obtain white signal components only, and the white-color
difference value is detected. The 8-bit single-chip microcomputer acquires this detection data, and
controls the R and B gains to produce the true white.
The State Data of the AWB detection is AWB_A0 and A8.
The AE-detection block divides the CCD output signal converted to digital by the 10-bit ADC to six
arbitrary areas, and performs integration processing. This function enables detection of the lighting
level of the image signal.
The 8-bit single-chip microcomputer acquires this detection data, and controls the accumulation
amount (the shutter) of the CCD sensor or the iris motor of the lens to maintain the proper lighting.
The State Data of the AF detection is AE_A0 to A7 and A8.
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