HD49815TF Datasheet, PDF (14/25 Pages) Hitachi Semiconductor – Digital Camera Signal Processor

HD49815TF
3. 8-bit single-chip microcomputer
The 8-bit single-chip microcomputer controls the system. It receives the image detection data that the
HD49815TF is gathering and implements automatic iris control (AE), automatic white balance control
(AWB), and automatic focus control (AF).
When setting the power on, this microcomputer implements the initial setting to the state data of the
HD49815TF.
For details on the state data, see “Hitachi Camera DSP (HD49815TF) State Data”.
Built-in Functions
1. Input line memory block
A/D input
10-bit
16
De-Knee
AGC
DL +
1HDL
16
Memory
control
1HDL
To the color-signal
processing block
To the luminance-signal
processing block
Figure 3 Input Line Memory Block
a. De-knee function
When the CDS/AGC IC at the pre-stage or the external circuit uses the knee circuit to expand the
dynamic range of the signal, the de-knee (inverse knee) circuit returns the signal converted by the
knee circuit to the original state.
The de-knee point can be set in State Data SP_A0 [1]. The gain of the high-luminance block is 1/2.
b. AGC function
A digital AGC circuit is provided. The AGC gain can be set in State Data SP_A0 [2] from 1 to 16
times.
c. 1H delay line (1HDL) function
This circuit obtains horizontal efficient pixels of the CCD output signal. The number of efficient
pixels is set in State Data SP_A0 [9, 10] and TM_A0 [14] MCSET.
14